Volume 4 128-Bit Media Instructions (794098), страница 40
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3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionDevice not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.General protection,#GPXInstruction ReferencePOR297AMD64 Technology26568—Rev.
3.09—July 2007PSADBWPacked Sum of Absolute Differences of Bytes Intoa WordComputes the absolute differences of eight corresponding packed 8-bit unsigned integers in the firstand second source operands and writes the unsigned 16-bit integer result of the sum of the eightdifferences in a word in the destination (first source). The first source/destination operand is an XMMregister and the second source operand is another XMM register or 128-bit memory location.The sum of the differences of the eight bytes in the high-order quadwords of the source operands arewritten in the least-significant word of the high-order quadword in the destination XMM register, withthe remaining bytes cleared to all 0s.
The sum of the differences of the eight bytes in the low-orderquadwords of the source operands are written in the least-significant word of the low-order quadwordin the destination XMM register, with the remaining bytes cleared to all 0s.The PSADBW instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePSADBW xmm1, xmm2/mem128DescriptionCompute the sum of the absolute differences of twosets of packed 8-bit unsigned integer values in anXMM register and another XMM register or 128-bitmemory location and writes the 16-bit unsigned integerresult in the destination XMM register.66 0F F6 /rxmm1127xmm2/mem128064 63...........64 63127.......0......absolutedifferenceabsolutedifferenceadd 8pairsabsolutedifferenceabsolutedifferenceadd 8pairs1277964 6301500psadbw-128.eps298PSADBWInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePSADBW299AMD64 Technology26568—Rev.
3.09—July 2007PSHUFDPacked Shuffle DoublewordsMoves any one of the four packed doublewords in an XMM register or 128-bit memory location toeach doubleword in another XMM register. In each case, the value of the destination doubleword isdetermined by a two-bit field in the immediate-byte operand, with bits 0 and 1 selecting the contents ofthe low-order doubleword, bits 2 and 3 selecting the second doubleword, bits 4 and 5 selecting the thirddoubleword, and bits 6 and 7 selecting the high-order doubleword.
Refer to Table 1-4 on page 301. Adoubleword in the source operand may be copied to more than one doubleword in the destination.The PSHUFD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePSHUFD xmm1, xmm2/mem128,imm8DescriptionMoves packed 32-bit values in an XMMregister or 128-bit memory location todoubleword locations in another XMMregister, as selected by the immediate-byteoperand.66 0F 70 /r ibxmm112796 9564 63xmm2/mem12832 31012796 9564 6332 310imm87 0muxmuxmuxmuxpshufd.eps300PSHUFDInstruction Reference26568—Rev. 3.09—July 2007Table 1-4.AMD64 TechnologyImmediate-Byte Operand Encoding for PSHUFDImmediate-ByteBit FieldDestination Bits Filled31–01–063–323–295–645–4127–967–6Value of Bit FieldSource Bits Moved031–0163–32295–643127–96031–0163–32295–643127–96031–0163–32295–643127–96031–0163–32295–643127–96Related InstructionsPSHUFHW, PSHUFLW, PSHUFWrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionInvalid opcode, #UDInstruction ReferenceRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.PSHUFD301AMD64 TechnologyException26568—Rev.
3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionDevice not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.General protection, #GPX302PSHUFDInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyPSHUFHWPacked Shuffle High WordsMoves any one of the four packed words in the high-order quadword of an XMM register or 128-bitmemory location to each word in the high-order quadword of another XMM register.
In each case, thevalue of the destination word is determined by a two-bit field in the immediate-byte operand, with bits0 and 1 selecting the contents of the low-order word, bits 2 and 3 selecting the second word, bits 4 and5 selecting the third word, and bits 6 and 7 selecting the high-order word. Refer to Table 1-5 onpage 304. A word in the source operand may be copied to more than one word in the destination. Thelow-order quadword of the source operand is copied to the low-order quadword of the destinationregister.The PSHUFHW instruction is an SSE2 instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePSHUFHW xmm1, xmm2/mem128, imm8DescriptionShuffles packed 16-bit values in highorder quadword of an XMM register or128-bit memory location and puts theresult in high-order quadword of anotherXMM register.F3 0F 70 /r ibxmm1127 112 111 96 95 80 79 64 63xmm2/mem1280127 112 111 96 95 80 79 64 630imm87 0muxmuxmuxmuxpshufhw.epsInstruction ReferencePSHUFHW303AMD64 TechnologyTable 1-5.26568—Rev.
3.09—July 2007Immediate-Byte Operand Encoding for PSHUFHWImmediate-ByteBit FieldDestination Bits Filled79–641–095–803–2111–965–4127–1127–6Value of Bit FieldSource Bits Moved079–64195–802111–963127–112079–64195–802111–963127–112079–64195–802111–963127–112079–64195–802111–963127–112Related InstructionsPSHUFD, PSHUFLW, PSHUFWrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionInvalid opcode, #UD304RealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.PSHUFHWInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionDevice not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.General protection, #GPXInstruction ReferencePSHUFHW305AMD64 Technology26568—Rev.
3.09—July 2007PSHUFLWPacked Shuffle Low WordsMoves any one of the four packed words in the low-order quadword of an XMM register or 128-bitmemory location to each word in the low-order quadword of another XMM register. In each case, theselection of the value of the destination word is determined by a two-bit field in the immediate-byteoperand, with bits 0 and 1 selecting the contents of the low-order word, bits 2 and 3 selecting thesecond word, bits 4 and 5 selecting the third word, and bits 6 and 7 selecting the high-order word.Refer to Table 1-6 on page 307. A word in the source operand may be copied to more than one word inthe destination. The high-order quadword of the source operand is copied to the high-order quadwordof the destination register.The PSHUFLW instruction is an SSE2 instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePSHUFLW xmm1, xmm2/mem128, imm8DescriptionShuffles packed 16-bit values in loworder quadword of an XMM register or128-bit memory location and puts theresult in low-order quadword of anotherXMM register.F2 0F 70 /r ibxmm1127xmm2/mem12864 63 48 47 32 31 16 15012764 63 48 47 32 31 16 150imm87 0muxmuxmuxmuxpshuflw.eps306PSHUFLWInstruction Reference26568—Rev.
3.09—July 2007Table 1-6.AMD64 TechnologyImmediate-Byte Operand Encoding for PSHUFLWImmediate-ByteBit FieldDestination Bits Filled15–01–031–163–247–325–463–487–6Value of Bit FieldSource Bits Moved015–0131–16247–32363–48015–0131–16247–32363–48015–0131–16247–32363–48015–0131–16247–32363–48Related InstructionsPSHUFD, PSHUFHW, PSHUFWrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionInvalid opcode, #UDInstruction ReferenceRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.PSHUFLW307AMD64 TechnologyException26568—Rev.
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