Volume 4 128-Bit Media Instructions (794098), страница 42
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3.09—July 2007PSRADAMD64 TechnologyPacked Shift Right Arithmetic DoublewordsRight-shifts each of the packed 32-bit values in the first source operand by the number of bits specifiedin the second source operand and writes each shifted value in the corresponding doubleword of thedestination (first source). The first source/destination and second source operands are:••an XMM register and another XMM register or 128-bit memory location, oran XMM register and an immediate byte value.The high-order bits that are emptied by the shift operation are filled with the sign bit of thedoubleword’s initial value. If the shift value is greater than 31, each doubleword in the destination isfilled with the sign bit of the doubleword’s initial value.The PSRAD instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionPSRAD xmm1,xmm2/mem12866 0F E2 /rRight-shifts packed doublewords in an XMM registerby the amount specified in the low 64 bits of an XMMregister or 128-bit memory location.PSRAD xmm, imm866 0F 72 /4 ibRight-shifts packed doublewords in an XMM registerby the amount specified in an immediate byte value.xmm112796 95.64 63.xmm2/mem128.32 31012764 630.shift rightshift rightxmm12796 95..64 63imm8.32 3107 0.shift rightshift rightpsrad-128.epsInstruction ReferencePSRAD317AMD64 Technology26568—Rev.
3.09—July 2007Related InstructionsPSLLD, PSLLDQ, PSLLQ, PSLLW, PSRAW, PSRLD, PSRLDQ, PSRLQ, PSRLWrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX318PSRADInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyPSRAWPacked Shift Right Arithmetic WordsRight-shifts each of the packed 16-bit values in the first source operand by the number of bits specifiedin the second source operand and writes each shifted value in the corresponding word of thedestination (first source). The first source/destination and second source operands are:••an XMM register and another XMM register or 128-bit memory location, oran XMM register and an immediate byte value.The high-order bits that are emptied by the shift operation are filled with the sign bit of the word’sinitial value. If the shift value is greater than 15, each word in the destination is filled with the sign bitof the word’s initial value.The PSRAW instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionPSRAW xmm1, xmm2/mem12866 0F E1 /rRight-shifts packed words in an XMM register by theamount specified in the low 64 bits of an XMMregister or 128-bit memory location.PSRAW xmm, imm866 0F 71 /4 ibRight-shifts packed words in an XMM register by theamount specified in an immediate byte value.xmm1...xmm2/mem128...127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....012764 630.shift rightarithmeticshift rightarithmeticxmm...imm8...127 112 111 96 95 80 79 64 63 48 47 32 31 16 15..shift rightarithmetic...07 0.shift rightarithmeticpsraw-128.epsInstruction ReferencePSRAW319AMD64 Technology26568—Rev. 3.09—July 2007Related InstructionsPSLLD, PSLLDQ, PSLLQ, PSLLW, PSRAD, PSRLD, PSRLDQ, PSRLQ, PSRLWrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX320PSRAWInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyPSRLDPacked Shift Right Logical DoublewordsRight-shifts each of the packed 32-bit values in the first source operand by the number of bits specifiedin the second source operand and writes each shifted value in the corresponding doubleword of thedestination (first source). The first source/destination and second source operands are:••an XMM register and another XMM register or 128-bit memory location, oran XMM register and an immediate byte value.The high-order bits that are emptied by the shift operation are cleared to 0.
If the shift value is greaterthan 31, the destination is cleared to 0.The PSRLD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionPSRLD xmm1,xmm2/mem12866 0F D2 /rRight-shifts packed doublewords in an XMM registerby the amount specified in the low 64 bits of an XMMregister or 128-bit memory location.PSRLD xmm, imm866 0F 72 /2 ibRight-shifts packed doublewords in an XMM registerby the amount specified in an immediate byte value.xmm112796 95.64 63.xmm2/mem128.32 31012764 630.shift rightshift rightxmm12796 95..64 63imm8.32 3107 0.shift rightshift rightpsrld-128.epsInstruction ReferencePSRLD321AMD64 Technology26568—Rev. 3.09—July 2007Related InstructionsPSLLD, PSLLDQ, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLDQ, PSRLQ, PSRLWrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX322PSRLDInstruction Reference26568—Rev.
3.09—July 2007PSRLDQAMD64 TechnologyPacked Shift Right Logical Double QuadwordRight-shifts the 128-bit (double quadword) value in an XMM register by the number of bytes specifiedin an immediate byte value. The high-order bytes that are emptied by the shift operation are cleared to0. If the shift value is greater than 15, the destination XMM register is cleared to all 0s.The PSRLDQ instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePSRLDQ xmm, imm8DescriptionRight-shifts double quadword value in an XMMregister by the amount specified in an immediate bytevalue.66 0F 73 /3 ibxmm127imm807 0shift rightpsrldq.epsRelated InstructionsPSLLD, PSLLDQ, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLQ, PSRLWrFLAGS AffectedNoneMXCSR Flags AffectedNoneInstruction ReferencePSRLDQ323AMD64 Technology26568—Rev.
3.09—July 2007ExceptionsExceptionInvalid opcode, #UDDevice not available,#NM324RealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.XXXThe task-switch bit (TS) of CR0 was set to 1.PSRLDQInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyPSRLQPacked Shift Right Logical QuadwordsRight-shifts each 64-bit value in the first source operand by the number of bits specified in the secondsource operand and writes each shifted value in the corresponding quadword of the destination (firstsource).
The first source/destination and second source operands are:••an XMM register and another XMM register or 128-bit memory location, oran XMM register and an immediate byte value.The high-order bits that are emptied by the shift operation are cleared to 0. If the shift value is greaterthan 63, the destination is cleared to 0.The PSRLQ instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionPSRLQ xmm1,xmm2/mem12866 0F D3 /rRight-shifts packed quadwords in an XMM register bythe amount specified in the low 64 bits of an XMMregister or 128-bit memory location.PSRLQ xmm, imm866 0F 73 /2 ibRight-shifts packed quadwords in an XMM register bythe amount specified in an immediate byte value.xmm1127xmm2/mem12864 63012764 630shift rightshift rightxmm127imm864 6307 0shift rightshift rightpsrlq-128.epsInstruction ReferencePSRLQ325AMD64 Technology26568—Rev.
3.09—July 2007Related InstructionsPSLLD, PSLLDQ, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLWrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX326PSRLQInstruction Reference26568—Rev.
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