Volume 4 128-Bit Media Instructions (794098), страница 38
Текст из файла (страница 38)
The first source/destination operand is an XMM register and the secondsource operand is another XMM register or 128-bit memory location.The PMADDWD instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodePMADDWD xmm1, xmm2/mem128DescriptionMultiplies eight packed 16-bit signed values in anXMM register and another XMM register or 128-bitmemory location, adds intermediate results, andwrites the result in the destination XMM register.66 0F F5 /rxmm1xmm2/mem128127 112 111 96 95 80 79 64 63 48 47 32 31 16 15...0127 112 111 96 95 80 79 64 63 48 47 32 31 16 15....0.multiplymultiplymultiplyaddmultiplyadd.12796 95.64 6332 310pmaddwd-128.epsThere is only one case in which the result of the multiplication and addition will not fit in a signed 32bit destination. If all four of the 16-bit source operands used to produce a 32-bit multiply-add resulthave the value 8000h, the 32-bit result is 8000_0000h, which is incorrect.Related InstructionsPMULHUW, PMULHW, PMULLW, PMULUDQ276PMADDWDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePMADDWD277AMD64 Technology26568—Rev.
3.09—July 2007PMAXSWPacked Maximum Signed WordsCompares each of the packed 16-bit signed integer values in the first source operand with thecorresponding packed 16-bit signed integer value in the second source operand and writes thenumerically greater of the two values for each comparison in the corresponding word of the destination(first source). The first source/destination and second source operands are an XMM register and anXMM register or 128-bit memory location.The PMAXSW instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePMAXSW xmm1, xmm2/mem128DescriptionCompares packed signed 16-bit integer values in an XMMregister and another XMM register or 128-bit memorylocation and writes the greater value of each comparisonin destination XMM register.66 0F EE/rxmm1....xmm2/mem128..127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....0127 112 111 96 95 80 79 64 63 48 47 32 31 16 15......0.maximummaximumpmaxsw-128.epsRelated InstructionsPMAXUB, PMINSW, PMINUBrFLAGS AffectedNoneMXCSR Flags AffectedNone278PMAXSWInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePMAXSW279AMD64 Technology26568—Rev.
3.09—July 2007PMAXUBPacked Maximum Unsigned BytesCompares each of the packed 8-bit unsigned integer values in the first source operand with thecorresponding packed 8-bit unsigned integer value in the second source operand and writes thenumerically greater of the two values for each comparison in the corresponding byte of the destination(first source). The first source/destination and second source operands are an XMM register and anXMM register or 128-bit memory location.The PMAXUB instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodePMAXUB xmm1, xmm2/mem128DescriptionCompares packed unsigned 8-bit integer values in anXMM register and another XMM register or 128-bitmemory location and writes the greater value of eachcompare in the destination XMM register.66 0F DE /rxmm1........xmm2/mem128......1270.............127.0..............maximummaximumpmaxub-128.epsRelated InstructionsPMAXSW, PMINSW, PMINUBrFLAGS AffectedNoneMXCSR Flags AffectedNone280PMAXUBInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePMAXUB281AMD64 Technology26568—Rev.
3.09—July 2007PMINSWPacked Minimum Signed WordsCompares each of the packed 16-bit signed integer values in the first source operand with thecorresponding packed 16-bit signed integer value in the second source operand and writes thenumerically lesser of the two values for each comparison in the corresponding word of the destination(first source). The first source/destination and second source operands are an XMM register and anXMM register or 128-bit memory location.The PMINSW instruction is an SSE instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePMINSW xmm1, xmm2/mem128Description66 0F EA /rCompares packed signed 16-bit integer values in anXMM register and another XMM register or 128-bitmemory location and writes the lesser value of eachcompare in the destination XMM register.xmm1....xmm2/mem128..127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....0127 112 111 96 95 80 79 64 63 48 47 32 31 16 15......0.minimumminimumpminsw-128.epsRelated InstructionsPMAXSW, PMAXUB, PMINUBrFLAGS AffectedNoneMXCSR Flags AffectedNone282PMINSWInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePMINSW283AMD64 Technology26568—Rev.
3.09—July 2007PMINUBPacked Minimum Unsigned BytesCompares each of the packed 8-bit unsigned integer values in the first source operand with thecorresponding packed 8-bit unsigned integer value in the second source operand and writes thenumerically lesser of the two values for each comparison in the corresponding byte of the destination(first source). The first source/destination operand is an XMM register and the second source operandis another XMM register or 128-bit memory location.The PMINUB instruction is an SSE instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePMINUB xmm1, xmm2/mem128DescriptionCompares packed unsigned 8-bit integer values in anXMM register and another XMM register or 128-bitmemory location and writes the lesser value of eachcomparison in the destination XMM register.66 0F DA /rxmm1........xmm2/mem128......1270..............1270..............minimumminimumpminub-128.epsRelated InstructionsPMAXSW, PMAXUB, PMINSWrFLAGS AffectedNoneMXCSR Flags AffectedNone284PMINUBInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePMINUB285AMD64 Technology26568—Rev.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
