Volume 4 128-Bit Media Instructions (794098), страница 36
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The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePAVGW xmm1, xmm2/mem128DescriptionAverages packed 16-bit unsigned integer values in anXMM register and another XMM register or 128-bitmemory location and writes the result in thedestination XMM register.66 0F E3 /rxmm1....xmm2/mem128..127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....0.127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....0.averageaveragepavgw-128.epsRelated InstructionsPAVGBrFLAGS AffectedNoneMXCSR Flags AffectedNone258PAVGWInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby bit 25 in CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePAVGW259AMD64 Technology26568—Rev.
3.09—July 2007PCMPEQBPacked Compare Equal BytesCompares corresponding packed bytes in the first and second source operands and writes the result ofeach comparison in the corresponding byte of the destination (first source). For each pair of bytes, ifthe values are equal, the result is all 1s. If the values are not equal, the result is all 0s. The firstsource/destination operand is an XMM register and the second source operand is another XMMregister or 128-bit memory location.The PCMPEQB instruction is an SSE2 instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePCMPEQB xmm1, xmm2/mem128DescriptionCompares packed bytes in an XMM register and anXMM register or 128-bit memory location.66 0F 74 /rxmm1........xmm2/mem128......1270.............127.0..............comparecompareall 1s or 0sall 1s or 0spcmpeqb-128.epsRelated InstructionsPCMPEQD, PCMPEQW, PCMPGTB, PCMPGTD, PCMPGTWrFLAGS AffectedNoneMXCSR Flags AffectedNone260PCMPEQBInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection,#GPXInstruction ReferencePCMPEQB261AMD64 Technology26568—Rev.
3.09—July 2007PCMPEQDPacked Compare Equal DoublewordsCompares corresponding packed 32-bit values in the first and second source operands and writes theresult of each comparison in the corresponding 32 bits of the destination (first source). For each pair ofdoublewords, if the values are equal, the result is all 1s. If the values are not equal, the result is all 0s.The first source/destination operand is an XMM register and the second source operand is anotherXMM register or 128-bit memory location.The PCMPEQD instruction is an SSE2 instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePCMPEQD xmm1,xmm2/mem128DescriptionCompares packed doublewords in an XMM registerand an XMM register or 128-bit memory location.66 0F 76 /rxmm1.12796 95xmm2/mem128.64 63.32 31012796 95.64 63.32 310.comparecompareall 1s or 0sall 1s or 0spcmpeqd-128.epsRelated InstructionsPCMPEQB, PCMPEQW, PCMPGTB, PCMPGTD, PCMPGTWrFLAGS AffectedNoneMXCSR Flags AffectedNone262PCMPEQDInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection,#GPXInstruction ReferencePCMPEQD263AMD64 Technology26568—Rev.
3.09—July 2007PCMPEQWPacked Compare Equal WordsCompares corresponding packed 16-bit values in the first and second source operands and writes theresult of each comparison in the corresponding 16 bits of the destination (first source). For each pair ofwords, if the values are equal, the result is all 1s. If the values are not equal, the result is all 0s. The firstsource/destination operand is an XMM register and the second source operand is another XMMregister or 128-bit memory location.The PCMPEQW instruction is an SSE2 instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePCMPEQW xmm1, xmm2/mem128DescriptionCompares packed 16-bit values in an XMM registerand an XMM register or 128-bit memory location.66 0F 75 /rxmm1....xmm2/mem128..127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....0127 112 111 96 95 80 79 64 63 48 47 32 31 16 15......0.comparecompareall 1s or 0sall 1s or 0spcmpeqw-128.epsRelated InstructionsPCMPEQB, PCMPEQD, PCMPGTB, PCMPGTD, PCMPGTWrFLAGS AffectedNoneMXCSR Flags AffectedNone264PCMPEQWInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection,#GPXInstruction ReferencePCMPEQW265AMD64 Technology26568—Rev.
3.09—July 2007PCMPGTBPacked Compare Greater Than Signed BytesCompares corresponding packed signed bytes in the first and second source operands and writes theresult of each comparison in the corresponding byte of the destination (first source). For each pair ofbytes, if the value in the first source operand is greater than the value in the second source operand, theresult is all 1s. If the value in the first source operand is less than or equal to the value in the secondsource operand, the result is all 0s. The first source/destination operand is an XMM register and thesecond source operand is another XMM register or 128-bit memory location.The PCMPGTB instruction is an SSE2 instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePCMPGTB xmm1, xmm2/mem128DescriptionCompares packed signed bytes in an XMM registerand an XMM register or 128-bit memory location.66 0F 64 /rxmm1127................xmm2/mem128............01270..............comparecompareall 1s or 0sall 1s or 0spcmpgtb-128.epsRelated InstructionsPCMPEQB, PCMPEQD, PCMPEQW, PCMPGTD, PCMPGTWrFLAGS AffectedNoneMXCSR Flags AffectedNone266PCMPGTBInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePCMPGTB267AMD64 Technology26568—Rev.
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