Volume 4 128-Bit Media Instructions (794098), страница 32
Текст из файла (страница 32)
The threehigh-order doublewords of the destination are not modified. The first source/destination operand is anXMM register. The second source operand is another XMM register or 32-bit memory location.The MULSS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeMULSS xmm1, xmm2/mem32DescriptionF3 0F 59 /rMultiplies low-order single-precision floating-point valuesin an XMM register and another XMM register or 32-bitmemory location and writes the result in the low-orderdoubleword of the destination XMM register.xmm1127xmm2/mem3232 31012732 310multiplymulss.epsRelated InstructionsMULPD, MULPS, MULSD, PFMULrFLAGS AffectedNoneInstruction ReferenceMULSS223AMD64 Technology26568—Rev.
3.09—July 2007MXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEMMM543ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN value.XXX±Zero was multiplied by ±infinity.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Underflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.224MULSSInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionDenormalized-operandexception (DE)XXXA source operand was a denormal value.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.Instruction ReferenceMULSS225AMD64 Technology26568—Rev. 3.09—July 2007ORPDLogical Bitwise ORPacked Double-Precision Floating-PointPerforms a bitwise logical OR of the two packed double-precision floating-point values in the firstsource operand and the corresponding two packed double-precision floating-point values in the secondsource operand and writes the result in the destination (first source).
The first source/destinationoperand is an XMM register. The second source operand is another XMM register or 128-bit memorylocation.The ORPD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeORPD xmm1,xmm2/mem12866 0F 56 /rDescriptionPerforms bitwise logical OR of two packed doubleprecision floating-point values in an XMM register and inanother XMM register or 128-bit memory location andwrites the result in the destination XMM register.xmm1127xmm2/mem12864 63012764 630ORORorpd.epsRelated InstructionsANDNPD, ANDNPS, ANDPD, ANDPS, ORPS, XORPD, XORPSrFLAGS AffectedNoneMXCSR Flags AffectedNone226ORPDInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MM wasset to 1.Invalid opcode, #UDGeneral protection,#GPXInstruction ReferenceORPD227AMD64 Technology26568—Rev.
3.09—July 2007ORPSLogical Bitwise ORPacked Single-Precision Floating-PointPerforms a bitwise logical OR of the four packed single-precision floating-point values in the firstsource operand and the corresponding four packed single-precision floating-point values in the secondsource operand and writes the result in the destination (first source). The first source/destinationoperand is an XMM register.
The second source operand is another XMM register or 128-bit memorylocation.The ORPS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeORPS xmm1,xmm2/mem128DescriptionPerforms bitwise logical OR of four packed single-precisionfloating-point values in an XMM register and in another XMMregister or 128-bit memory location and writes the result in thedestination XMM register.0F 56 /rxmm112796 95xmm2/mem12864 6332 31012796 9564 6332 310ORORORORorps.epsRelated InstructionsANDNPD, ANDNPS, ANDPD, ANDPS, ORPD, XORPD, XORPSrFLAGS AffectedNoneMXCSR Flags AffectedNone228ORPSInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MM wasset to 1.Invalid opcode, #UDGeneral protection,#GPXInstruction ReferenceORPS229AMD64 Technology26568—Rev.
3.09—July 2007PACKSSDWPack with Saturation Signed Doubleword to WordConverts each 32-bit signed integer in the first and second source operands to a 16-bit signed integerand packs the converted values into words in the destination (first source). The first source/destinationoperand is an XMM register and the second source operand is another XMM register or 128-bitmemory location.Converted values from the first source operand are packed into the low-order words of the destination,and the converted values from the second source operand are packed into the high-order words of thedestination.The PACKSSDW instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePACKSSDW xmm1, xmm2/mem128Description66 0F 6B /rPacks 32-bit signed integers in an XMM registerand another XMM register or 128-bit memorylocation into 16-bit signed integers in an XMMregister.xmm112796 95xmm2/mem12864 63.32 31012796 95.64 63.convertconvert.0.convert.32 31convert..127 112 111 96 95 80 79 64 63 48 47 32 31 16 150packssdw-128.epsFor each packed value in the destination, if the value is larger than the largest signed 16-bit integer, it issaturated to 7FFFh, and if the value is smaller than the smallest signed 16-bit integer, it is saturated to8000h.Related InstructionsPACKSSWB, PACKUSWBrFLAGS AffectedNone230PACKSSDWInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePACKSSDW231AMD64 Technology26568—Rev.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
