Volume 4 128-Bit Media Instructions (794098), страница 29
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The processor treats the store as a write-combining memory write, which minimizes cachepollution.Support for the MOVNTSD instruction is indicated by ECX bit 6 (SSE4A) as returned by CPUIDfunction 8000_0001h. Software must check the CPUID bit once per program or library initializationbefore using the MOVNTSD instruction or inconsistent behavior may result.MnemonicMOVNTSDOpcodemem64, xmmDescriptionStores one double-precision floating-point XMMregister value into a 64 bit memory location.
Treat asa non-temporal store.F2 0F 2B /rmem6463xmm012764 630copyRelated InstructionsMOVNTDQ, MOVNTI, MOVNTPD, MOVNTPS, MOVNTQ, MOVNTSSrFLAGS AffectedNone192MOVNTSDInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE4A instructions are not supported, asindicated by ECX bit 6 (SSE4A) of CPUID function8000_0001h.XXXThe emulate bit (CR0.EM) was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(CR4.OSFXSR) was cleared to 0.Device not available,#NMXXXThe task-switch bit (CR0.TS) was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.Invalid opcode, #UDGeneral protection,#GPPage fault, #PFXXA page fault resulted from executing the instruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceMOVNTSD193AMD64 Technology26568—Rev.
3.09—July 2007MOVNTSSMove Non-Temporal ScalarSingle-Precision Floating-PointStores one single-precision floating-point XMM register value into a 32-bit memory location. Thisinstruction indicates to the processor that the data is non-temporal, and is unlikely to be used againsoon. The processor treats the store as a write-combining memory write, which minimizes cachepollution.Support for the MOVNTSS instruction is indicated by ECX bit 6 (SSE4A) as returned by CPUIDfunction 8000_0001h. Software must check the CPUID bit once per program or library initializationbefore using the MOVNTSS instruction, or inconsistent behavior may result.MnemonicMOVNTSSOpcodemem32, xmmDescriptionStores one single-precision floating-point XMMregister value into a 32-bit memory location. Treat asa non-temporal store.F3 0F 2B /rmem3231xmm0311270copyRelated InstructionsMOVNTDQ, MOVNTI, MOVNTOPD, MOVNTPS, MOVNTQ, MOVNTSDrFLAGS AffectedNone194MOVNTSSInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE4A instructions are not supported, asindicated by ECX bit 6 (SSE4A) of CPUID function8000_0001h.XXXThe emulate bit (CR0.EM) was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(CR4.OSFXSR) was cleared to 0.Device not available,#NMXXXThe task-switch bit (CR0.TS) was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.Invalid opcode, #UDGeneral protection,#GPPage fault, #PFXXA page fault resulted from executing the instruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceMOVNTSS195AMD64 Technology26568—Rev.
3.09—July 2007MOVQMove QuadwordMoves a 64-bit value in one of the following ways:••from the low-order 64 bits of an XMM register or a 64-bit memory location to the low-order 64 bitsof another XMM register, with zero-extension to 128 bitsfrom the low-order 64 bits of an XMM register to the low-order 64 bits of another XMM register,with zero-extension to 128 bits or to a 64-bit memory locationThe MOVQ instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionMOVQ xmm1, xmm2/mem64F3 0F 7E /rMoves 64-bit value from an XMM register or memorylocation to an XMM register.MOVQ xmm1/mem64, xmm266 0F D6 /rMoves 64-bit value from an XMM register to an XMMregister or memory location.xmm112764 63xmm2/mem64012764 6300copyxmm1/mem6412764 63xmm2012764 6300copymovq-128.epsRelated InstructionsMOVD, MOVDQA, MOVDQU, MOVDQ2Q, MOVQ2DQrFLAGS AffectedNone196MOVQInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.Invalid opcode, #UDGeneral protection,#GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceMOVQ197AMD64 Technology26568—Rev.
3.09—July 2007MOVQ2DQMove Quadword to QuadwordMoves a 64-bit value from an MMX register to the low-order 64 bits of an XMM register, with zeroextension to 128 bits.The MOVQ2DQ instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeMOVQ2DQ xmm, mmxF3 0F D6 /rDescriptionMoves 64-bit value from an MMX™ register to an XMMregister.xmm127mmx64 6306300copymovq2dq.epsRelated InstructionsMOVD, MOVDQA, MOVDQU, MOVDQ2Q, MOVQrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionInvalid opcode, #UD198RealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.MOVQ2DQInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionDevice not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.x87 floating-pointexception pending,#MFXXXAn exception was pending due to an x87 floating-pointinstruction.Instruction ReferenceMOVQ2DQ199AMD64 TechnologyMOVSD26568—Rev. 3.09—July 2007Move Scalar Double-Precision Floating-PointMoves a scalar double-precision floating-point value:••from the low-order 64 bits of an XMM register or a 64-bit memory location to the low-order 64 bitsof another XMM register, orfrom the low-order 64 bits of an XMM register to the low-order 64 bits of another XMM register ora 64-bit memory location.If the source operand is an XMM register, the high-order 64 bits of the destination XMM register arenot modified. If the source operand is a memory location, the high-order 64 bits of the destinationXMM register are cleared to all 0s.This MOVSD instruction should not be confused with the MOVSD (move string doubleword)instruction with the same mnemonic in the general-purpose instruction set.
Assemblers can distinguishthe instructions by the number and type of operands.The MOVSD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionMOVSD xmm1, xmm2/mem64F2 0F 10 /rMoves double-precision floating-point value from anXMM register or 64-bit memory location to an XMMregister.MOVSD xmm1/mem64, xmm2F2 0F 11 /rMoves double-precision floating-point value from anXMM register to an XMM register or 64-bit memorylocation.200MOVSDInstruction Reference26568—Rev.
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