Volume 4 128-Bit Media Instructions (794098), страница 26
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3.09—July 2007AMD64 TechnologyMOVDMove Doubleword or QuadwordMoves a 32-bit or 64-bit value in one of the following ways:••••from a 32-bit or 64-bit general-purpose register or memory location to the low-order 32 or 64 bitsof an XMM register, with zero-extension to 128 bitsfrom the low-order 32 or 64 bits of an XMM to a 32-bit or 64-bit general-purpose register ormemory locationfrom a 32-bit or 64-bit general-purpose register or memory location to the low-order 32 bits (withzero-extension to 64 bits) or the full 64 bits of an MMX registerfrom the low-order 32 or the full 64 bits of an MMX register to a 32-bit or 64-bit general-purposeregister or memory locationThe MOVD instruction is an MMX instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionMOVD xmm, reg/mem3266 0F 6E /rMove 32-bit value from a general-purpose register or32-bit memory location to an XMM register.MOVD xmm, reg/mem6466 0F 6E /rMove 64-bit value from a general-purpose register or64-bit memory location to an XMM register.MOVD reg/mem32, xmm66 0F 7E /rMove 32-bit value from an XMM register to a 32-bitgeneral-purpose register or memory location.MOVD reg/mem64, xmm66 0F 7E /rMove 64-bit value from an XMM register to a 64-bitgeneral-purpose register or memory location.Instruction ReferenceMOVD159AMD64 Technology26568—Rev.
3.09—July 2007xmmreg/mem3212732 3131000xmm127reg/mem6464 6363000with REX prefixreg/mem32All operationsare "copy"310xmm12732 31reg/mem64630xmm012764 630with REX prefixmmx6332 31reg/mem3231000mmx63reg/mem640630with REX prefixreg/mem3231mmx063reg/mem64630mmx063with REX prefix16032 31MOVD0movd.epsInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyRelated InstructionsMOVDQA, MOVDQU, MOVDQ2Q, MOVQ, MOVQ2DQrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptions (All Modes)RealVirtual8086ProtectedXXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 of CPUID function0000_0001h.XXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe instruction used XMM registers whileCR4.OSFXSR=0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.General protection,#GPXXXA memory address exceeded a data segment limit orwas non-canonical.XXA page fault resulted from the execution of theinstruction.XXAn x87 floating-point exception was pending and theinstruction referenced an MMX register.XXAn unaligned memory reference was performed whilealignment checking was enabled.ExceptionInvalid opcode, #UDPage fault, #PFx87 floating-pointexception pending,#MFAlignment check, #ACInstruction ReferenceXDescriptionMOVD161AMD64 Technology26568—Rev.
3.09—July 2007MOVDDUPMove Double-Precision and DuplicateMoves a quadword value with its duplicate from the source operand to each quadword half of theXMM destination operand. The source operand may be an XMM register or the address of the leastsignificant byte of 64 bits of data in memory. When an XMM register is specified as the sourceoperand, the lower 64-bits are duplicated and copied. When a memory address is specified, the 8 bytesof data at mem64 are duplicated and loaded.The MOVDDUP instruction is an SSE3 instruction. The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeMOVDDUP xmm1,xmm2/mem64F2 0F 12 /rDescriptionMoves two copies of the lower 64 bits of the sourceXMM or 128-bit memory operand to the lower and upperquadwords of the destination XMM register.xmm112764 63xmm2/mem64012864 630Related InstructionsMOVSHDUP, MOVSLDUPrFLAGS AffectedNoneMXCSR Flags AffectedNone162MOVDDUPInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE3 instructions are not supported, asindicated by ECX bit 0 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceMOVDDUP163AMD64 Technology26568—Rev.
3.09—July 2007MOVDQ2QMove Quadword to QuadwordMoves the low-order 64-bit value in an XMM register to a 64-bit MMX register.The MOVDQ2Q instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeMOVDQ2Q mmx, xmmDescriptionMoves low-order 64-bit value from an XMM register to thedestination MMX register.F2 0F D6 /rmmxxmm63012764 630copymovdq2q.epsRelated InstructionsMOVD, MOVDQA, MOVDQU, MOVQ, MOVQ2DQrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionInvalid opcode, #UDDevice not available,#NM164RealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.XXXThe task-switch bit (TS) of CR0 was set to 1.MOVDQ2QInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedGeneral protectionx87 floating-pointexception pending,#MFInstruction ReferenceXXCause of ExceptionXThe destination operand was in a non-writablesegment.XAn exception was pending due to an x87 floating-pointinstruction.MOVDQ2Q165AMD64 Technology26568—Rev. 3.09—July 2007MOVDQAMove Aligned Double QuadwordMoves an aligned 128-bit (double quadword) value:••from an XMM register or 128-bit memory location to another XMM register, orfrom an XMM register to a 128-bit memory location or another XMM register.A memory operand that is not aligned on a 16-byte boundary causes a general-protection exception.The MOVDQA instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionMOVDQA xmm1, xmm2/mem12866 0F 6F /rMoves 128-bit value from an XMM register or 128-bitmemory location to the destination XMM register.MOVDQA xmm1/mem128, xmm266 0F 7F /rMoves 128-bit value from an XMM register to thedestination XMM register or 128-bit memory location.xmm1127xmm2/mem12801270copyxmm1/mem128127xmm201270copymovdqa.epsRelated InstructionsMOVD, MOVDQU, MOVDQ2Q, MOVQ, MOVQ2DQrFLAGS AffectedNone166MOVDQAInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.XXThe memory operand was not aligned on a 16-byteboundary.XXA page fault resulted from the execution of theinstruction.Invalid opcode, #UDGeneral protection,#GPXPage fault, #PFInstruction ReferenceMOVDQA167AMD64 Technology26568—Rev.
3.09—July 2007MOVDQUMove Unaligned Double QuadwordMoves an unaligned 128-bit (double quadword) value:••from an XMM register or 128-bit memory location to another XMM register, orfrom an XMM register to another XMM register or 128-bit memory location.Memory operands that are not aligned on a 16-byte boundary do not cause a general-protectionexception.The MOVDQU instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionMOVDQU xmm1, xmm2/mem128F3 0F 6F /rMoves 128-bit value from an XMM register orunaligned 128-bit memory location to thedestination XMM register.MOVDQU xmm1/mem128, xmm2F3 0F 7F /rMoves 128-bit value from an XMM register to thedestination XMM register or unaligned 128-bitmemory location.xmm1127xmm2/mem12801270copyxmm1/mem128127xmm201270copymovdqu.epsRelated InstructionsMOVD, MOVDQA, MOVDQ2Q, MOVQ, MOVQ2DQrFLAGS AffectedNone168MOVDQUInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedNoneExceptionsRealVirtual8086ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.ExceptionInvalid opcode, #UDGeneral protection,#GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceMOVDQU169AMD64 Technology26568—Rev.
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