Volume 4 128-Bit Media Instructions (794098), страница 25
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Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN or QNaN value.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Instruction ReferenceMINPS149AMD64 TechnologyMINSD26568—Rev.
3.09—July 2007Minimum Scalar Double-Precision Floating-PointCompares the double-precision floating-point value in the low-order 64 bits of the first source operandwith the double-precision floating-point value in the low-order 64 bits of the second source operandand writes the numerically lesser of the two values in the low-order 64 bits of the destination (firstsource). The first source/destination operand is an XMM register.
The second source operand isanother XMM register or a 64-bit memory location. The high-order quadword of the destination XMMregister is not modified.If both source operands are equal to zero, the value in the second source operand is returned. If eitheroperand is a NaN (SNaN or QNaN), and invalid-operation exceptions are masked, the second sourceoperand is written to the destination.The MINSD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeMINSD xmm1, xmm2/mem64F2 0F 5D /rDescriptionCompares scalar double-precision floating-point values inan XMM register and another XMM register or 64-bitmemory location and writes the lesser of the two valuesin the destination XMM register.xmm1127xmm2/mem6464 63012764 630minimumminsd.epsRelated InstructionsMAXPD, MAXPS, MAXSD, MAXSS, MINPD, MINPS, MINSSrFLAGS AffectedNone150MINSDInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZPE65UE4OEZE32DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN or QNaN value.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Instruction ReferenceMINSD151AMD64 TechnologyMINSS26568—Rev.
3.09—July 2007Minimum Scalar Single-Precision Floating-PointCompares the single-precision floating-point value in the low-order 32 bits of the first source operandwith the single-precision floating-point value in the low-order 32 bits of the second source operand andwrites the numerically lesser of the two values in the low-order 32 bits of the destination (first source).The first source/destination operand is an XMM register.
The second source operand is another XMMregister or a 32-bit memory location. The three high-order doublewords of the destination XMMregister are not modified.If both source operands are equal to zero, the value in the second source operand is returned. If eitheroperand is a NaN (SNaN or QNaN), and invalid-operation exceptions are masked, the second sourceoperand is written to the destination.The MINSS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeMINSS xmm1, xmm2/mem32DescriptionF3 0F 5D /rCompares scalar single-precision floating-point values inan XMM register and another XMM register or 32-bitmemory location and writes the lesser of the two values inthe destination XMM register.xmm1127xmm2/mem3232 31012732 310minimumminss.epsRelated InstructionsMAXPD, MAXPS, MAXSD, MAXSS, MINPD, MINPS, MINSDrFLAGS AffectedNone152MINSSInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZPE65UE4OEZE32DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN or QNaN value.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Instruction ReferenceMINSS153AMD64 Technology26568—Rev.
3.09—July 2007MOVAPDMove Aligned Packed Double-PrecisionFloating-PointMoves two packed double-precision floating-point values:••from an XMM register or 128-bit memory location to another XMM register, orfrom an XMM register to another XMM register or 128-bit memory location.A memory operand that is not aligned on a 16-byte boundary causes a general-protection exception.The MOVAPD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionMOVAPD xmm1, xmm2/mem12866 0F 28 /rMoves packed double-precision floating-point valuefrom an XMM register or 128-bit memory location toan XMM register.MOVAPD xmm1/mem128, xmm266 0F 29 /rMoves packed double-precision floating-point valuefrom an XMM register to an XMM register or 128-bitmemory location.xmm112764 63xmm2/mem128012764 630copycopyxmm1/mem12812764 63xmm2012764 630copycopymovapd.epsRelated InstructionsMOVHPD, MOVLPD, MOVMSKPD, MOVSD, MOVUPD154MOVAPDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limit orwas non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.XXThe memory operand was not aligned on a 16-byteboundary.XXA page fault resulted from the execution of theinstruction.Invalid opcode, #UDGeneral protection,#GPXPage fault, #PFInstruction ReferenceMOVAPD155AMD64 TechnologyMOVAPS26568—Rev.
3.09—July 2007Move Aligned Packed Single-PrecisionFloating-PointMoves four packed single-precision floating-point values:••from an XMM register or 128-bit memory location to another XMM register, orfrom an XMM register to another XMM register or 128-bit memory location.The MOVAPS instruction is an SSE instruction; check the status of EDX bit 25 returned by CPUIDfunction 0000_0001h to verify that the processor supports this function. (See “CPUID” in Volume 3.)A memory operand that is not aligned on a 16-byte boundary causes a general-protection exception.MnemonicOpcodeDescriptionMOVAPS xmm1, xmm2/mem1280F 28 /rMoves aligned packed single-precision floating-pointvalue from an XMM register or 128-bit memory locationto the destination XMM register.MOVAPS xmm1/mem128, xmm20F 29 /rMoves aligned packed single-precision floating-pointvalue from an XMM register to the destination XMMregister or 128-bit memory location.156MOVAPSInstruction Reference26568—Rev.
3.09—July 2007AMD64 Technologyxmm112796 9564 63xmm2/mem12832 31012796 9564 6332 310copycopycopycopyxmm1/mem12812796 9564 63xmm232 31012796 9564 6332 310copycopycopycopymovaps.epsRelated InstructionsMOVHLPS, MOVHPS, MOVLHPS, MOVLPS, MOVMSKPS, MOVSS, MOVUPSrFLAGS AffectedNoneMXCSR Flags AffectedNoneInstruction ReferenceMOVAPS157AMD64 Technology26568—Rev.
3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limit orwas non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.XXThe memory operand was not aligned on a 16-byteboundary.XXA page fault resulted from the execution of theinstruction.Invalid opcode, #UDGeneral protection,#GPXPage fault, #PF158MOVAPSInstruction Reference26568—Rev.
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