Volume 4 128-Bit Media Instructions (794098), страница 20
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The bit index and field length are each six bits in length;other bits of the field are ignored.Support for the EXTRQ instruction is indicated by ECX bit 6 (SSE4A) as returned by CPUID function8000_0001h. Software must check the CPUID bit once per program or library initialization beforeusing the EXTRQ instruction, or inconsistent behavior may result.MnemonicEXTRQ xmm1, imm8, imm8EXTRQ xmm1, xmm2112OpcodeDescription66 0F 78 /0 ib ibExtract field from xmm1, with the least significant bitof the extracted data starting at the bit indexspecified by [5:0] of the second immediate byte, withthe length specified by [5:0] of the first immediatebyte.66 0F 79 /rExtract field from xmm1, with the least significant bitof the extracted data starting at the bit indexspecified by xmm2[13:8], with the length specifiedby xmm2[5:0].EXTRQInstruction Reference26568—Rev.
3.09—July 2007AMD64 Technologyxmm1127second imm864 637 500first imm87 50shift rightmask to field lengthxmm1127xmm264 63012713 85 0shift rightmask to field lengthRelated InstructionsINSERTQ, PINSRW, PEXTRWrFLAGS AffectedNoneExceptionsExceptionInvalid opcode, #UDDevice not available,#NMInstruction ReferenceRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE4A instructions are not supported, asindicated by ECX bit 6 (SSE4A) of CPUID function8000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 is cleared to 0.XXXThe task-switch bit (TS) of CR0 was set to 1.EXTRQ113AMD64 Technology26568—Rev.
3.09—July 2007FXRSTORRestore XMM, MMX, and x87 StateRestores the XMM, MMX, and x87 state. The data loaded from memory is the state informationpreviously saved using the FXSAVE instruction. Restoring data with FXRSTOR that had beenpreviously saved with an FSAVE (rather than FXSAVE) instruction results in an incorrect restoration.If FXRSTOR results in set exception flags in the loaded x87 status word register, and these exceptionsare unmasked in the x87 control word register, a floating-point exception occurs when the nextfloating-point instruction is executed (except for the no-wait floating-point instructions).If the restored MXCSR register contains a set bit in an exception status flag, and the correspondingexception mask bit is cleared (indicating an unmasked exception), loading the MXCSR register frommemory does not cause a SIMD floating-point exception (#XF).FXRSTOR does not restore the x87 error pointers (last instruction pointer, last data pointer, and lastopcode), except in the relatively rare cases in which the exception-summary (ES) bit in the x87 statusword is set to 1, indicating that an unmasked x87 exception has occurred.The architecture supports two 512-bit memory formats for FXRSTOR, a 64-bit format that loadsXMM0-XMM15, and a 32-bit legacy format that loads only XMM0-XMM7.
If FXRSTOR is executedin 64-bit mode, the 64-bit format is used, otherwise the 32-bit format is used. When the 64-bit format isused, if the operand-size is 64-bit, FXRSTOR loads the x87 pointer registers as offset64, otherwise itloads them as sel:offset32. For details about the memory format used by FXRSTOR, see "SavingMedia and x87 Processor State" in Volume 2.If the fast-FXSAVE/FXRSTOR (FFXSR) feature is enabled in EFER, FXRSTOR does not restore theXMM registers (XMM0-XMM15) when executed in 64-bit mode at CPL 0.
MXCSR is restoredwhether fast-FXSAVE/FXRSTOR is enabled or not. Software can use CPUID to determine whetherthe fast-FXSAVE/FXRSTOR feature is available. (See “CPUID” in Volume 3.)If the operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0, the savedimage of XMM0–XMM15 and MXCSR is not loaded into the processor. A general-protectionexception occurs if the FXRSTOR instruction attempts to load non-zero values into reserved MXCSRbits. Software can use MXCSR_MASK to determine which bits of MXCSR are reserved. For detailson the MXCSR_MASK, see “128-Bit, 64-Bit, and x87 Programming” in Volume 2..MnemonicFXRSTOR mem512envOpcode0F AE /1DescriptionRestores XMM, MMX™, and x87 state from 512-bytememory location.Related InstructionsFWAIT, FXSAVErFLAGS AffectedNone114FXRSTORInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMMFZRCMMM171514PMUMOMZMDMIMDAZPEUEOEZEDEIEMMMMMMMMMMMMMM131211109876543210Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe FXSAVE/FXRSTOR instructions are notsupported, as indicated by EDX bit 24 of CPUIDfunction 0000_0001h or function 8000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFInstruction ReferenceXXXThe memory operand was not aligned on a 16-byteboundary.XXXOnes were written to the reserved bits in MXCSR.XXA page fault resulted from the execution of theinstruction.FXRSTOR115AMD64 Technology26568—Rev.
3.09—July 2007FXSAVESave XMM, MMX, and x87 StateSaves the XMM, MMX, and x87 state. A memory location that is not aligned on a 16-byte boundarycauses a general-protection exception.Unlike FSAVE and FNSAVE, FXSAVE does not alter the x87 tag bits. The contents of the savedMMX/x87 data registers are retained, thus indicating that the registers may be valid (or whatever othervalue the x87 tag bits indicated prior to the save). To invalidate the contents of the MMX/x87 dataregisters after FXSAVE, software must execute an FINIT instruction.
Also, FXSAVE (like FNSAVE)does not check for pending unmasked x87 floating-point exceptions. An FWAIT instruction can beused for this purpose.FXSAVE does not save the x87 pointer registers (last instruction pointer, last data pointer, and lastopcode), except in the relatively rare cases in which the exception-summary (ES) bit in the x87 statusword is set to 1, indicating that an unmasked x87 exception has occurred.The architecture supports two 512-bit memory formats for FXSAVE, a 64-bit format that savesXMM0-XMM15, and a 32-bit legacy format that saves only XMM0-XMM7.
If FXSAVE is executedin 64-bit mode, the 64-bit format is used, otherwise the 32-bit format is used. When the 64-bit format isused, if the operand-size is 64-bit, FXSAVE saves the x87 pointer registers as offset64, otherwise itsaves them as sel:offset32. For more details about the memory format used by FXSAVE, see “SavingMedia and x87 Processor State” in Volume 2.If the fast-FXSAVE/FXRSTOR (FFXSR) feature is enabled in EFER, FXSAVE does not save theXMM registers (XMM0-XMM15) when executed in 64-bit mode at CPL 0.
MXCSR is saved whetherfast-FXSAVE/FXRSTOR is enabled or not. Software can use CPUID to determine whether the fastFXSAVE/FXRSTOR feature is available. (See “CPUID” in Volume 3.)If the operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0, FXSAVEdoes not save the image of XMM0–XMM15 or MXCSR. For details about the CR4.OSFXSR bit, see“FXSAVE/FXRSTOR Support (OSFXSR) Bit” in Volume 2.MnemonicFXSAVE mem512envOpcode0F AE /0DescriptionSaves XMM, MMX, and x87 state to 512-byte memorylocation.Related InstructionsFINIT, FNSAVE, FRSTOR, FSAVE, FXRSTOR, LDMXCSR, STMXCSRrFLAGS AffectedNoneMXCSR Flags AffectedNone116FXSAVEInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe FXSAVE/FXRSTOR instructions are notsupported, as indicated by EDX bit 24 of CPUIDfunction 0000_0001h or function 8000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.XXThe memory operand was not aligned on a 16-byteboundary.XXA page fault resulted from the execution of theinstruction.Invalid opcode, #UDGeneral protection, #GPXPage fault, #PFInstruction ReferenceFXSAVE117AMD64 Technology26568—Rev.
3.09—July 2007HADDPDHorizontal Add Packed DoubleAdds the double-precision floating-point values in the high and low quadwords of the destinationoperand and stores the result in the low quadword of the destination operand. Simultaneously, theinstruction adds the double-precision floating-point values in the high and low quadwords of thesource operand and stores the result in the high quadword of the destination operand.The HADDPD instruction is an SSE3 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeHADDPD xmm1,xmm2/mem12866 0F 7C /rDescriptionAdds two packed double-precision values in xmm1 andstores the result in the lower 64 bits of xmm1; adds twopacked double-precision values in xmm2 or a 128-bitmemory operand and stores the result in the upper 64bits of xmm1.xmm1127xmm2/mem12864 63012764 630addaddRelated InstructionsHADDPS, HSUBPD, HSUBPSrFLAGS AffectedNone118HADDPDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM9IM87DAZ6PEUEOEMMM543ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE3 instructions are not supported, asindicated by ECX bit 0 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions below for details.General protection, #GPXSIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsXXXA source operand was an SNaN value.XXX+infinity was added to –infinity.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Invalid-operationexception (IE)Instruction ReferenceHADDPD119AMD64 TechnologyException26568—Rev.
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