Volume 4 128-Bit Media Instructions (794098), страница 19
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Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Overflow exception (OE)104XXXA source operand was an SNaN value.XXX±Zero was divided by ±zero.XXX±infinity was divided by ±infinity.XXXA rounded result was too large to fit into the format ofthe destination operand.DIVPSInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionUnderflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Zero-divide exception(ZE)XXXA non-zero number was divided by zero.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.Instruction ReferenceDIVPS105AMD64 Technology26568—Rev. 3.09—July 2007DIVSDDivide Scalar Double-Precision Floating-PointDivides the double-precision floating-point value in the low-order quadword of the first sourceoperand by the double-precision floating-point value in the low-order quadword of the second sourceoperand and writes the result in the low-order quadword of the destination (first source).
The highorder quadword of the destination is not modified. The first source/destination operand is an XMMregister. The second source operand is another XMM register or 128-bit memory location.The DIVSD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDIVSD xmm1, xmm2/mem64F2 0F 5E /rDescriptionDivides low-order double-precision floating-point value inan XMM register by the low-order double-precisionfloating-point value in another XMM register or in a 64- or128-bit memory location.xmm1127xmm2/mem6464 63012764 630dividedivsd.epsRelated InstructionsDIVPD, DIVPS, DIVSSrFLAGS AffectedNone106DIVSDInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEZEDEIEMMMMMM543210Note: A flag that may be set to one or cleared to zero is M (modified).
Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsXXXA source operand was an SNaN value.XXX±Zero was divided by ±zero.XXX±infinity was divided by ±infinity.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Underflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.Invalid-operationexception (IE)Instruction ReferenceDIVSD107AMD64 TechnologyException26568—Rev.
3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionDenormalized-operandexception (DE)XXXA source operand was a denormal value.Zero-divide exception(ZE)XXXA non-zero number was divided by zero.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.108DIVSDInstruction Reference26568—Rev. 3.09—July 2007DIVSSAMD64 TechnologyDivide Scalar Single-Precision Floating-PointDivides the single-precision floating-point value in the low-order doubleword of the first sourceoperand by the single-precision floating-point value in the low-order doubleword of the second sourceoperand and writes the result in the low-order doubleword of the destination (first source). The threehigh-order doublewords of the destination are not modified. The first source/destination operand is anXMM register. The second source operand is another XMM register or 128-bit memory location.The DIVSS instruction is an SSE instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDIVSS xmm1, xmm2/mem32DescriptionF3 0F 5E /rDivides low-order single-precision floating-point value inan XMM register by the low-order single-precisionfloating-point value in another XMM register or in a 32-bitmemory location.xmm1127xmm2/mem3232 31012732 310dividedivss.epsRelated InstructionsDIVPD, DIVPS, DIVSDrFLAGS AffectedNoneInstruction ReferenceDIVSS109AMD64 Technology26568—Rev.
3.09—July 2007MXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEZEDEIEMMMMMM543210Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsXXXA source operand was an SNaN value.XXX±Zero was divided by ±zero.XXX±infinity was divided by ±infinity.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Underflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Invalid-operationexception (IE)110DIVSSInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionZero-divide exception(ZE)XXXA non-zero number was divided by zero.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.Instruction ReferenceDIVSS111AMD64 Technology26568—Rev. 3.09—July 2007EXTRQExtract Field From RegisterExtracts specified bits from the lower 64 bits of the first operand (the destination XMM register). Theextracted bits are saved in the least-significant bit positions of the destination; the remaining bits in thelower 64 bits of the destination register are cleared to 0.
The upper 64 bits of the destination register areundefined.The portion of the source data being extracted is defined by the bit index and the field length. The bitindex defines the least-significant bit of the source operand being extracted. Bits [bit index + lengthfield – 1]:[bit index] are extracted. If the sum of the bit index + length field is greater than 64, the resultsare undefined.For example, if the bit index is 32 (20h) and the field length is 16 (10h), then the result in thedestination register will be source [47:32] in bits 15:0, with zeros in bits 63:16.A value of zero in the field length is defined as a length of 64.
If the length field is 0 and thebit index is 0, bits 63:0 of the source are extracted. For any other value of the bit index, the results areundefined.The bit index and field length can be specified as immediate values (second and first immediateoperands, respectively, in the case of the three argument version of the instruction), or they can both bespecified by fields in an XMM source operand. In the latter case, bits [5:0] of the XMM registerspecify the number of bits to extract (the field length) and bits [13:8] of the XMM register specify theindex of the first bit in the field to extract.
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