Volume 4 128-Bit Media Instructions (794098), страница 16
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3.09—July 2007Convert Scalar Single-Precision Floating-Pointto Scalar Double-Precision Floating-PointConverts a single-precision floating-point value in the low-order 32 bits of an XMM register or a 32-bitmemory location to a double-precision floating-point value and writes the converted value in the loworder 64 bits of another XMM register. The high-order 64 bits in the destination XMM register are notmodified.The CVTSS2SD instruction is an SSE2 instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTSS2SD xmm1, xmm2/mem32DescriptionConverts scalar single-precision floating-point valuein an XMM register or 32-bit memory location todouble-precision floating-point value in thedestination XMM register.F3 0F 5A /rxmm112764 63xmm2/mem32012732 310convertcvtss2sd.epsRelated InstructionsCVTPD2PS, CVTPS2PD, CVTSD2SSrFLAGS AffectedNone80CVTSS2SDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZPE65UE4OEZE32DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN value.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Instruction ReferenceCVTSS2SD81AMD64 TechnologyCVTSS2SI26568—Rev.
3.09—July 2007Convert Scalar Single-Precision Floating-Pointto Signed Doubleword or Quadword IntegerThe CVTSS2SI instruction converts a single-precision floating-point value in the low-order 32 bits ofan XMM register or a 32-bit memory location to a 32-bit or 64-bit signed integer value and writes theconverted value in a general-purpose register.If the result of the conversion is an inexact value, the value is rounded as specified by the roundingcontrol bits (RC) in the MXCSR register. If the floating-point value is a NaN, infinity, or if the result ofthe conversion is larger than the maximum signed doubleword (–231 to +231 – 1) or quadword value(–263 to +263 – 1), the instruction returns the indefinite integer value (8000_0000h for 32-bit integers,8000_0000_0000_0000h for 64-bit integers) when the invalid-operation exception (IE) is masked.The CVTSS2SI instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionCVTSS2SI reg32,xmm2/mem32F3 0F 2D /rConverts a single-precision floating-point value in anXMM register or 32-bit memory location to adoubleword integer value in a general-purpose register.CVTSS2SI reg64,xmm2/mem32F3 0F 2D /rConverts a single-precision floating-point value in anXMM register or 32-bit memory location to a quadwordinteger value in a general-purpose register.reg3231xmm2/mem32012732 310convertreg6463xmm2/mem32012732 310convertwith REX prefix82CVTSS2SIcvtss2si.epsInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyRelated InstructionsCVTDQ2PS, CVTPI2PS, CVTPS2DQ, CVTPS2PI, CVTSI2SS, CVTTPS2DQ, CVTTPS2PI,CVTTSS2SIrFLAGS AffectedNoneMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEM1715141312111098765IEM43210Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFInstruction ReferenceXCVTSS2SI83AMD64 TechnologyException26568—Rev.
3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Precision exception(PE)84XXXA source operand was an SNaN value, a QNaNvalue, or ±infinity.XXXA source operand was too large to fit in thedestination format.XXXA result could not be represented exactly in thedestination format.CVTSS2SIInstruction Reference26568—Rev. 3.09—July 2007CVTTPD2DQAMD64 TechnologyConvert Packed Double-Precision Floating-Pointto Packed Doubleword Integers, TruncatedConverts two packed double-precision floating-point values in an XMM register or a 128-bit memorylocation to two packed 32-bit signed integer values and writes the converted values in the low-order 64bits of another XMM register.
The high-order 64 bits of the destination XMM register are cleared to all0s.If the result of the conversion is an inexact value, the value is truncated (rounded toward zero). If thefloating-point value is a NaN, infinity, or if the result of the conversion is larger than the maximumsigned doubleword (–231 to +231 – 1), the instruction returns the 32-bit indefinite integer value(8000_0000h) when the invalid-operation exception (IE) is masked.The CVTTPD2DQ instruction is an SSE2 instruction.
The presence of this instruction set is indicatedby a CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTTPD2DQ xmm1, xmm2/mem128DescriptionConverts packed double-precision floating-pointvalues in an XMM register or 128-bit memorylocation to packed doubleword integer values inthe destination XMM register. Inexact results aretruncated.66 0F E6 /rxmm112764 63xmm2/mem12832 31012764 6300convertconvertcvttpd2dq.epsRelated InstructionsCVTDQ2PD, CVTPD2DQ, CVTPD2PI, CVTPI2PD, CVTSD2SI, CVTSI2SD, CVTTPD2PI,CVTTSD2SIrFLAGS AffectedNoneInstruction ReferenceCVTTPD2DQ85AMD64 Technology26568—Rev. 3.09—July 2007MXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEM1715141312111098765IEM43210Note: A flag that may be set to one or cleared to zero is M (modified).
Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Precision exception(PE)86XXXA source operand was an SNaN value, a QNaNvalue, or ±infinity.XXXA source operand was too large to fit in thedestination format.XXXA result could not be represented exactly in thedestination format.CVTTPD2DQInstruction Reference26568—Rev.
3.09—July 2007CVTTPD2PIAMD64 TechnologyConvert Packed Double-Precision Floating-Pointto Packed Doubleword Integers, TruncatedConverts two packed double-precision floating-point values in an XMM register or a 128-bit memorylocation to two packed 32-bit signed integer values and writes the converted values in an MMXregister.If the result of the conversion is an inexact value, the value is truncated (rounded toward zero). If thefloating-point value is a NaN, infinity, or if the result of the conversion is larger than the maximumsigned doubleword (–231 to +231 – 1), the instruction returns the 32-bit indefinite integer value(8000_0000h) when the invalid-operation exception (IE) is masked.The CVTTPD2PI instruction is an SSE2 instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTTPD2PI mmx,xmm/mem12866 0F 2C /rDescriptionConverts packed double-precision floating-point valuesin an XMM register or 128-bit memory location topacked doubleword integer values in the destinationMMX register. Inexact results are truncated.mmx6332 31xmm/mem128012764 63convert0convertcvttpd2pi.epsRelated InstructionsCVTDQ2PD, CVTPD2DQ, CVTPD2PI, CVTPI2PD, CVTSD2SI, CVTSI2SD, CVTTPD2DQ,CVTTSD2SIrFLAGS AffectedNoneInstruction ReferenceCVTTPD2PI87AMD64 Technology26568—Rev. 3.09—July 2007MXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEM1715141312111098765IEM43210Note: A flag that may be set to one or cleared to zero is M (modified).
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