Volume 4 128-Bit Media Instructions (794098), страница 12
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(See “CPUID” in Volume 3.)MnemonicOpcodeCOMISS xmm1, xmm2/mem32Description0F 2F /rCompares single-precision floating-point values in an XMMregister and an XMM register or 32-bit memory location.Sets rFLAGS.xmm1xmm2/mem32127310127310compare63310Result of Compare0rFLAGScomiss.epsZFPFCFUnordered111Greater Than000Less Than001Equal100Related InstructionsCMPPD, CMPPS, CMPSD, CMPSS, COMISD, UCOMISD, UCOMISSInstruction ReferenceCOMISS45AMD64 Technology26568—Rev. 3.09—July 2007rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCF0M0MM7642002120191817161413–12111098Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified).
Unaffected flags are blank.Note: If the instruction causes an unmasked SIMD floating-point exception (#XF), the rFLAGS bits are not updated.MXCSR Flags AffectedMM17FZ15RC14PM1312UM11OM10ZMDM98IM7DAZ6PE5UE4OEZE32DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XF46XXCOMISSInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN or QNaN value.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Instruction ReferenceCOMISS47AMD64 TechnologyCVTDQ2PD26568—Rev.
3.09—July 2007Convert Packed Doubleword Integers to PackedDouble-Precision Floating-PointConverts two packed 32-bit signed integer values in the low-order 64 bits of an XMM register or a 64bit memory location to two packed double-precision floating-point values and writes the convertedvalues in another XMM register.The CVTDQ2PD instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTDQ2PD xmm1, xmm2/mem64DescriptionConverts packed doubleword signed integers in anXMM register or 64-bit memory location to doubleprecision floating-point values in the destination XMMregister.F3 0F E6 /rxmm112764 63xmm2/mem64012764 6332 310convertconvertcvtdq2pd.epsRelated InstructionsCVTPD2DQ, CVTPD2PI, CVTPI2PD, CVTSD2SI, CVTSI2SD, CVTTPD2DQ, CVTTPD2PI,CVTTSD2SIrFLAGS AffectedNoneMXCSR Flags AffectedNone48CVTDQ2PDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceCVTDQ2PD49AMD64 TechnologyCVTDQ2PS26568—Rev.
3.09—July 2007Convert Packed Doubleword Integers to PackedSingle-Precision Floating-PointConverts four packed 32-bit signed integer values in an XMM register or a 128-bit memory location tofour packed single-precision floating-point values and writes the converted values in another XMMregister. If the result of the conversion is an inexact value, the value is rounded as specified by therounding control bits (RC) in the MXCSR register.The CVTDQ2PS instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTDQ2PS xmm1, xmm2/mem128DescriptionConverts packed doubleword integer values in anXMM register or 128-bit memory location to packedsingle-precision floating-point values in the destinationXMM register.0F 5B /rxmm112796 9564 63xmm2/mem12832 31012796 9564 6332 310convertconvertconvertconvertcvtdq2ps.epsRelated InstructionsCVTPI2PS, CVTPS2DQ, CVTPS2PI, CVTSI2SS, CVTSS2SI, CVTTPS2DQ, CVTTPS2PI,CVTTSS2SIrFLAGS AffectedNone50CVTDQ2PSInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEIE43210M1715141312111098765Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsPrecision exception(PE)Instruction ReferenceXXXA result could not be represented exactly in thedestination format.CVTDQ2PS51AMD64 Technology26568—Rev.
3.09—July 2007CVTPD2DQ Convert Packed Double-Precision Floating-Point toPacked Doubleword IntegersConverts two packed double-precision floating-point values in an XMM register or a 128-bit memorylocation to two packed 32-bit signed integers and writes the converted values in the low-order 64 bitsof another XMM register. The high-order 64 bits in the destination XMM register are cleared to all 0s.If the result of the conversion is an inexact value, the value is rounded as specified by the roundingcontrol bits (RC) in the MXCSR register. If the floating-point value is a NaN, infinity, or if the result ofthe conversion is larger than the maximum signed doubleword (–231 to +231 – 1), the instructionreturns the 32-bit indefinite integer value (8000_0000h) when the invalid-operation exception (IE) ismasked.The CVTPD2DQ instruction is an SSE2 instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTPD2DQ xmm1, xmm2/mem128DescriptionConverts packed double-precision floating-pointvalues in an XMM register or 128-bit memorylocation to packed doubleword integers in thedestination XMM register.F2 0F E6 /rxmm112764 63xmm2/mem12832 31012764 6300convertconvertcvtpd2dq.epsRelated InstructionsCVTDQ2PD, CVTPD2PI, CVTPI2PD, CVTSD2SI, CVTSI2SD, CVTTPD2DQ, CVTTPD2PI,CVTTSD2SIrFLAGS AffectedNone52CVTPD2DQInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEM1715141312111098765IEM43210Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Precision exception(PE)Instruction ReferenceXXXA source operand was an SNaN value, a QNaNvalue, or ±infinity.XXXA source operand was too large to fit in thedestination format.XXXA result could not be represented exactly in thedestination format.CVTPD2DQ53AMD64 TechnologyCVTPD2PI26568—Rev.
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