Volume 4 128-Bit Media Instructions (794098), страница 9
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3.09—July 2007AMD64 TechnologyANDNPSLogical Bitwise AND NOTPacked Single-Precision Floating-PointPerforms a bitwise logical AND of the four packed single-precision floating-point values in the secondsource operand and the one’s-complement of the corresponding four packed single-precision floatingpoint values in the first source operand and writes the result in the destination (first source).
The firstsource/destination operand is an XMM register. The second source operand is another XMM registeror 128-bit memory location.The ADDNPS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeANDNPS xmm1,xmm2/mem128DescriptionPerforms bitwise logical AND NOT of four packed singleprecision floating-point values in an XMM register and inanother XMM register or 128-bit memory location andwrites the result in the destination XMM register.0F 55 /rxmm112796 95xmm2/mem12864 6332 31012796 9564 6332 310invertinvertANDinvertANDinvertANDANDandnps.epsRelated InstructionsANDNPD, ANDPD, ANDPS, ORPD, ORPS, XORPD, XORPSrFLAGS AffectedNoneMXCSR Flags AffectedNoneInstruction ReferenceANDNPS23AMD64 Technology26568—Rev.
3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limit orwas non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MM wasset to 1.Invalid opcode, #UDGeneral protection,#GPX24ANDNPSInstruction Reference26568—Rev.
3.09—July 2007ANDPDAMD64 TechnologyLogical Bitwise ANDPacked Double-Precision Floating-PointPerforms a bitwise logical AND of the two packed double-precision floating-point values in the firstsource operand and the corresponding two packed double-precision floating-point values in the secondsource operand and writes the result in the destination (first source). The first source/destinationoperand is an XMM register. The second source operand is another XMM register or 128-bit memorylocation.The ANDPD instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeANDPD xmm1, xmm2/mem12866 0F 54 /rDescriptionPerforms bitwise logical AND of two packed doubleprecision floating-point values in an XMM register and inanother XMM register or 128-bit memory location andwrites the result in the destination XMM register.xmm1127xmm2/mem12864 63012764 630ANDANDandpd.epsRelated InstructionsANDNPD, ANDNPS, ANDPS, ORPD, ORPS, XORPD, XORPSrFLAGS AffectedNoneMXCSR Flags AffectedNoneInstruction ReferenceANDPD25AMD64 Technology26568—Rev. 3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limit orwas non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MM wasset to 1.Invalid opcode, #UDGeneral protection,#GPX26ANDPDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyANDPSLogical Bitwise ANDPacked Single-Precision Floating-PointPerforms a bitwise logical AND of the four packed single-precision floating-point values in the firstsource operand and the corresponding four packed single-precision floating-point values in the secondsource operand and writes the result in the destination (first source). The first source/destinationoperand is an XMM register. The second source operand is another XMM register or 128-bit memorylocation.The ADDPS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeANDPS xmm1,xmm2/mem1280F 54 /rDescriptionPerforms bitwise logical AND of four packed single-precisionfloating-point values in an XMM register and in another XMMregister or 128-bit memory location and writes the result inthe destination XMM register.xmm112796 95xmm2/mem12864 6332 31012796 9564 6332 310ANDANDANDANDandps.epsRelated InstructionsANDNPD, ANDNPS, ANDPD, ORPD, ORPS, XORPD, XORPSrFLAGS AffectedNoneMXCSR Flags AffectedNoneInstruction ReferenceANDPS27AMD64 Technology26568—Rev. 3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicated byEDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limit orwas non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MM wasset to 1.Invalid opcode, #UDGeneral protection,#GPX28ANDPSInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyCMPPDCompare Packed Double-PrecisionFloating-PointCompares each of the two packed double-precision floating-point values in the first source operandwith the corresponding packed double-precision floating-point value in the second source operand andwrites the result of each comparison in the corresponding 64 bits of the destination (first source). Thetype of comparison is specified by the three low-order bits of the immediate-byte operand, as shown inTable 1-1. The result of each compare is a 64-bit value of all 1s (TRUE) or all 0s (FALSE). The firstsource/destination operand is an XMM register.
The second source operand is another XMM registeror 128-bit memory location.Signed compares return TRUE only if both operands are valid numbers, and the numbers have therelation specified by the type of compare. "Ordered" compare returns TRUE if both operands are validnumbers, or FALSE if either operand is a NaN. "Unordered" compare returns TRUE only if one orboth operands are NaN, and FALSE otherwise.QNaN operands generate an Invalid Operation Exception only if the compare type isn't "Equal","Unequal", "Ordered", or "Unordered".
SNaN operands always generate an Invalid OperationException (IE).Some comparison operations that are not directly supported by the immediate-byte encodings can beimplemented by swapping the contents of the source and destination operands and then executing theappropriate compare instruction using the swapped values.
These additional comparison operationsare shown, together with the directly supported comparison operations, in Table 1-1. When swappingoperands, the first source XMM register is overwritten by the result.The CMPPD instruction with appropriate value of imm8 is aliased to the following mnemonics tofacilitate coding with this instruction.MnemonicInstruction ReferenceImplied Value ofimm8CMPEQPD0CMPLTPD1CMPLEPD2CMPUNORDPD3CMPNEQPD4CMPNLTPD5CMPNLEPD6CMPORDPD7CMPPD29AMD64 Technology26568—Rev. 3.09—July 2007The CMPPD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCMPPD xmm1, xmm2/mem128,imm8DescriptionCompares two pairs of packed doubleprecision floating-point values in an XMMregister and an XMM register or 128-bitmemory location.66 0F C2 /r ibxmm112764 63xmm2/mem128012764 630imm87 0comparecompareall 1s or 0sall 1s or 0scmppd.eps30CMPPDInstruction Reference26568—Rev.
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