Volume 4 128-Bit Media Instructions (794098), страница 7
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Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions below for details.General protection, #GPXSIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsXXXA source operand was an SNaN value.XXX+infinity was added to –infinity.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Invalid-operationexception (IE)4ADDPDInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionUnderflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.Instruction ReferenceADDPD5AMD64 Technology26568—Rev. 3.09—July 2007ADDPSAdd Packed Single-Precision Floating-PointAdds each packed single-precision floating-point value in the first source operand to thecorresponding packed single-precision floating-point value in the second source operand and writesthe result of each addition in the corresponding quadword of the destination (first source). The firstsource/destination operand is an XMM register. The second source operand is another XMM registeror 128-bit memory location.The ADDPS instruction is an SSE instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeADDPS xmm1, xmm2/mem1280F 58 /rDescriptionAdds four packed single-precision floating-point values inan XMM register and another XMM register or 128-bitmemory location and writes the result in the destinationXMM register.xmm112796 95xmm2/mem12864 6332 31012796 9564 6332 310addaddaddaddaddps.epsRelated InstructionsADDPD, ADDSD, ADDSSrFLAGS AffectedNone6ADDPSInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEMMM543ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsXXXA source operand was an SNaN value.XXX+infinity was added to –infinity.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Invalid-operationexception (IE)Instruction ReferenceADDPS7AMD64 TechnologyException26568—Rev.
3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionUnderflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.8ADDPSInstruction Reference26568—Rev. 3.09—July 2007ADDSDAMD64 TechnologyAdd Scalar Double-Precision Floating-PointAdds the double-precision floating-point value in the low-order quadword of the first source operandto the double-precision floating-point value in the low-order quadword of the second source operandand writes the result in the low-order quadword of the destination (first source). The high-orderquadword of the destination is not modified. The first source/destination operand is an XMM register.The second source operand is another XMM register or 64-bit memory location.The ADDSD instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeADDSD xmm1, xmm2/mem64F2 0F 58 /rDescriptionAdds low-order double-precision floating-point values inan XMM register and another XMM register or 64-bitmemory location and writes the result in the destinationXMM register.xmm1127xmm2/mem6464 63012764 630addaddsd.epsRelated InstructionsADDPD, ADDPS, ADDSSrFLAGS AffectedNoneInstruction ReferenceADDSD9AMD64 Technology26568—Rev.
3.09—July 2007MXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEMMM543ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsXXXA source operand was an SNaN value.XXX+infinity was added to –infinity.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Invalid-operationexception (IE)10ADDSDInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionUnderflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.Instruction ReferenceADDSD11AMD64 Technology26568—Rev. 3.09—July 2007ADDSSAdd Scalar Single-Precision Floating-PointAdds the single-precision floating-point value in the low-order doubleword of the first source operandto the single-precision floating-point value in the low-order doubleword of the second source operandand writes the result in the low-order doubleword of the destination (first source).
The three high-orderdoublewords of the destination are not modified. The first source/destination operand is an XMMregister. The second source operand is another XMM register or 32-bit memory location.The ADDSS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeADDSS xmm1, xmm2/mem32DescriptionF3 0F 58 /rAdds low-order single-precision floating-point values inan XMM register and another XMM register or 32-bitmemory location and writes the result in the destinationXMM register.xmm1127xmm2/mem3232 31012732 310addaddss.epsRelated InstructionsADDPD, ADDPS, ADDSDrFLAGS AffectedNone12ADDSSInstruction Reference26568—Rev.
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