Volume 4 128-Bit Media Instructions (794098), страница 11
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Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Denormalized-operandexception (DE)38XXXA source operand was an SNaN value.XXXA source operand was a QNaN value, and thecomparison does not allow QNaN values (refer toTable 1-1 on page 31).XXXA source operand was a denormal value.CMPSDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyCMPSSCompare Scalar Single-PrecisionFloating-PointCompares the single-precision floating-point value in the low-order 32 bits of the first source operandwith the single-precision floating-point value in the low-order 32 bits of the second source operand andwrites the result in the low-order 32 bits of the destination (first source).
The type of comparison isspecified by the three low-order bits of the immediate-byte operand, as shown in Table 1-1 on page 31.The result of the compare is a 32-bit value of all 1s (TRUE) or all 0s (FALSE). The firstsource/destination operand is an XMM register. The second source operand is another XMM registeror 32-bit memory location. The three high-order doublewords of the destination XMM register are notmodified.Signed compares return TRUE only if both operands are valid numbers, and the numbers have therelation specified by the type of compare. "Ordered" compare returns TRUE if both operands are validnumbers, or FALSE if either operand is a NaN. "Unordered" compare returns TRUE only if one orboth operands are NaN, and FALSE otherwise.QNaN operands generate an Invalid Operation Exception only if the compare type isn't "Equal","Unequal", "Ordered", or "Unordered".
SNaN operands always generate an Invalid OperationException (IE).Some comparison operations that are not directly supported by the immediate-byte encodings can beimplemented by swapping the contents of the source and destination operands and then executing theappropriate compare instruction using the swapped values. These additional comparison operationsare shown in Table 1-1 on page 31. When swapping operands, the first source XMM register isoverwritten by the result.The CMPSS instruction with appropriate value of imm8 is aliased to the following mnemonics tofacilitate coding with this instruction.MnemonicInstruction ReferenceImplied Value ofimm8CMPEQSS0CMPLTSS1CMPLESS2CMPUNORDSS3CMPNEQSS4CMPNLTSS5CMPNLESS6CMPORDSS7CMPSS39AMD64 Technology26568—Rev.
3.09—July 2007The CMPSS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCMPSS xmm1, xmm2/mem32,imm8DescriptionCompares single-precision floating-pointvalues in an XMM register and an XMMregister or 32-bit memory location.F3 0F C2 /r ibxmm1127xmm2/mem3232 31012732 310imm87 0comparecmpss.epsRelated InstructionsCMPPD, CMPPS, CMPSD, COMISD, COMISS, UCOMISD, UCOMISSrFLAGS AffectedNone40CMPSSInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZPE65UE4OEZE32DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified).
Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Denormalized-operandexception (DE)Instruction ReferenceXXXA source operand was an SNaN value.XXXA source operand was a QNaN value, and thecomparison does not allow QNaN values (refer toTable 1-1 on page 31).XXXA source operand was a denormal value.CMPSS41AMD64 Technology26568—Rev.
3.09—July 2007COMISDCompare Ordered Scalar Double-PrecisionFloating-PointCompares the double-precision floating-point value in the low-order 64 bits of an XMM register withthe double-precision floating-point value in the low-order 64 bits of another XMM register or a 64-bitmemory location and sets the ZF, PF, and CF bits in the rFLAGS register to reflect the result of thecomparison. The OF, AF, and SF bits in rFLAGS are set to zero. The result is unordered if one or bothof the operand values is a NaN.If the instruction causes an unmasked SIMD floating-point exception (#XF), the rFLAGS bits are notupdated.The COMISD instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCOMISD xmm1, xmm2/mem64DescriptionCompares double-precision floating-point values in anXMM register and an XMM register or 64-bit memorylocation and sets rFLAGS.66 0F 2F /rxmm1127xmm2/mem6464 63012764 630compare63310Result of Compare0rFLAGScomisd.epsZFPFCFUnordered111Greater Than000Less Than001Equal100Related InstructionsCMPPD, CMPPS, CMPSD, CMPSS, COMISS, UCOMISD, UCOMISS42COMISDInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCF0M0MM7642002120191817161413–12111098Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Note: If the instruction causes an unmasked SIMD floating-point exception (#XF), the rFLAGS bits are not updated.MXCSR Flags AffectedMM17FZ15RC14PM1312UM11OM10ZMDM98IM7DAZ6PE5UE4OEZE32DEIEMM10Note: A flag that may be set either to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFInstruction ReferenceXCOMISD43AMD64 TechnologyException26568—Rev.
3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN or QNaN value.Denormalized-operandexception (DE)XXXA source operand was a denormal value.44COMISDInstruction Reference26568—Rev. 3.09—July 2007COMISSAMD64 TechnologyCompare Ordered Scalar Single-PrecisionFloating-PointPerforms an ordered comparison of the single-precision floating-point value in the low-order 32 bits ofan XMM register with the single-precision floating-point value in the low-order 32 bits of anotherXMM register or a 32-bit memory location and sets the ZF, PF, and CF bits in the rFLAGS register toreflect the result of the comparison.
The OF, AF, and SF bits in rFLAGS are set to zero. The result isunordered if one or both of the operand values is a NaN.If the instruction causes an unmasked SIMD floating-point exception (#XF), the rFLAGS bits are notupdated.The COMISS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit.
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