Volume 4 128-Bit Media Instructions (794098), страница 15
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3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Precision exception(PE)72XXXA source operand was an SNaN value, a QNaNvalue, or ±infinity.XXXA source operand was too large to fit in thedestination format.XXXA result could not be represented exactly in thedestination format.CVTSD2SIInstruction Reference26568—Rev. 3.09—July 2007CVTSD2SSAMD64 TechnologyConvert Scalar Double-Precision Floating-Pointto Scalar Single-Precision Floating-PointConverts a scalar double-precision floating-point value in the low-order 64 bits of an XMM register ora 64-bit memory location to a single-precision floating-point value and writes the converted value inthe low-order 32 bits of another XMM register.
The three high-order doublewords in the destinationXMM register are not modified. If the result of the conversion is an inexact value, the value is roundedas specified by the rounding control bits (RC) in the MXCSR register.The CVTSD2SS instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTSD2SS xmm1, xmm2/mem64DescriptionConverts a scalar double-precision floating-pointvalue in an XMM register or 64-bit memory locationto a scalar single-precision floating-point value inthe destination XMM register.F2 0F 5A /rxmm1127xmm2/mem6432 31012764 630convertcvtsd2ss.epsRelated InstructionsCVTPD2PS, CVTPS2PD, CVTSS2SDrFLAGS AffectedNoneInstruction ReferenceCVTSD2SS73AMD64 Technology26568—Rev.
3.09—July 2007MXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEMMM543ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN value.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Underflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.74CVTSD2SSInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionDenormalized-operandexception (DE)XXXA source operand was a denormal value.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.Instruction ReferenceCVTSD2SS75AMD64 TechnologyCVTSI2SD26568—Rev. 3.09—July 2007Convert Signed Doubleword or QuadwordInteger to Scalar Double-Precision Floating-PointConverts a 32-bit or 64-bit signed integer value in a general-purpose register or memory location to adouble-precision floating-point value and writes the converted value in the low-order 64 bits of anXMM register.
The high-order 64 bits in the destination XMM register are not modified.If the result of the conversion is an inexact value, the value is rounded as specified by the roundingcontrol bits (RC) in the MXCSR register.The CVTSI2SD instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionCVTSI2SD xmm, reg/mem32F2 0F 2A /rConverts a doubleword integer in a general-purposeregister or 32-bit memory location to a double-precisionfloating-point value in the destination XMM register.CVTSI2SD xmm, reg/mem64F2 0F 2A /rConverts a quadword integer in a general-purposeregister or 64-bit memory location to a double-precisionfloating-point value in the destination XMM register.xmm12764 63reg/mem323100convertxmm12764 63reg/mem640630convertwith REX prefixcvtsi2sd.epsRelated InstructionsCVTDQ2PD, CVTPD2DQ, CVTPD2PI, CVTPI2PD, CVTSD2SI, CVTTPD2DQ, CVTTPD2PI,CVTTSD2SI76CVTSI2SDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyrFLAGS AffectedNoneMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEIE43210M1715141312111098765Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsPrecision exception(PE)Instruction ReferenceXXXA result could not be represented exactly in thedestination format.CVTSI2SD77AMD64 TechnologyCVTSI2SS26568—Rev.
3.09—July 2007Convert Signed Doubleword or Quadword Integerto Scalar Single-Precision Floating-PointConverts a 32-bit or 64-bit signed integer value in a general-purpose register or memory location to asingle-precision floating-point value and writes the converted value in the low-order 32 bits of anXMM register. The three high-order doublewords in the destination XMM register are not modified.If the result of the conversion is an inexact value, the value is rounded as specified by the roundingcontrol bits (RC) in the MXCSR register.The CVTSI2SS instruction is an SSE instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionCVTSI2SS xmm, reg/mem32F3 0F 2A /rConverts a doubleword integer in a general-purposeregister or 32-bit memory location to a single-precisionfloating-point value in the destination XMM register.CVTSI2SS xmm, reg/mem64F3 0F 2A /rConverts a quadword integer in a general-purpose registeror 64-bit memory location to a single-precision floatingpoint value in the destination XMM register.xmm127reg/mem3232 313100convertxmm127reg/mem6432 310630convertwith REX prefixcvtsi2ss.epsRelated InstructionsCVTDQ2PS, CVTPI2PS, CVTPS2DQ, CVTPS2PI, CVTSS2SI, CVTTPS2DQ, CVTTPS2PI,CVTTSS2SI78CVTSI2SSInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyrFLAGS AffectedNoneMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEIE43210M1715141312111098765Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsPrecision exception(PE)Instruction ReferenceXXXA result could not be represented exactly in thedestination format.CVTSI2SS79AMD64 TechnologyCVTSS2SD26568—Rev.
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