Volume 4 128-Bit Media Instructions (794098), страница 14
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The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTPS2DQ xmm1, xmm2/mem128DescriptionConverts four packed single-precision floating-pointvalues in an XMM register or 128-bit memorylocation to four packed doubleword integers in thedestination XMM register.66 0F 5B /rxmm112796 9564 63xmm2/mem12832 31012796 9564 6332 310convertconvertconvertconvertcvtps2dq.epsRelated InstructionsCVTDQ2PS, CVTPI2PS, CVTPS2PI, CVTSI2SS, CVTSS2SI, CVTTPS2DQ, CVTTPS2PI,CVTTSS2SIrFLAGS AffectedNone64CVTPS2DQInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEM1715141312111098765IEM43210Note: A flag that may be set to one or cleared to zero is M (modified).
Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Precision exception(PE)Instruction ReferenceXXXA source operand was an SNaN value, a QNaNvalue, or ±infinity.XXXA source operand was too large to fit in thedestination format.XXXA result could not be represented exactly in thedestination format.CVTPS2DQ65AMD64 TechnologyCVTPS2PD26568—Rev.
3.09—July 2007Convert Packed Single-Precision Floating-Pointto Packed Double-Precision Floating-PointConverts two packed single-precision floating-point values in the low-order 64 bits of an XMMregister or a 64-bit memory location to two packed double-precision floating-point values and writesthe converted values in another XMM register.The CVTPS2PD instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeCVTPS2PD xmm1,xmm2/mem640F 5A /rDescriptionConverts packed single-precision floating-point values inan XMM register or 64-bit memory location to packeddouble-precision floating-point values in the destinationXMM register.xmm112764 63xmm2/mem64012764 6332 31convert0convertcvtps2pd.epsRelated InstructionsCVTPD2PS, CVTSD2SS, CVTSS2SDrFLAGS AffectedNone66CVTPS2PDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZPE65UE4OEZE32DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN value.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Instruction ReferenceCVTPS2PD67AMD64 TechnologyCVTPS2PI26568—Rev.
3.09—July 2007Convert Packed Single-Precision Floating-Point toPacked Doubleword IntegersConverts two packed single-precision floating-point values in the low-order 64 bits of an XMMregister or a 64-bit memory location to two packed 32-bit signed integers and writes the convertedvalues in an MMX register.If the result of the conversion is an inexact value, the value is rounded as specified by the roundingcontrol bits (RC) in the MXCSR register. If the floating-point value is a NaN, infinity, or if the result ofthe conversion is larger than the maximum signed doubleword (–231 to +231 – 1), the instructionreturns the 32-bit indefinite integer value (8000_0000h) when the invalid-operation exception (IE) ismasked.The CVTPS2PI instruction is an SSE instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTPS2PI mmx,xmm/mem640F 2D /rDescriptionConverts packed single-precision floating-point values in anXMM register or 64-bit memory location to packeddoubleword integers in the destination MMX register.mmx6332 31xmm/mem64012764 6332 31convert0convertcvtps2pi.epsRelated InstructionsCVTDQ2PS, CVTPI2PS, CVTPS2DQ, CVTSI2SS, CVTSS2SI, CVTTPS2DQ, CVTTPS2PI,CVTTSS2SIrFLAGS AffectedNone68CVTPS2PIInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEM1715141312111098765IEM43210Note: A flag that may be set to one or cleared to zero is M (modified).
Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn exception was pending due to an x87 floatingpoint instruction.XXAn unaligned memory reference was performedwhile alignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFXAlignment check, #ACSIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Precision exception(PE)Instruction ReferenceXXXA source operand was an SNaN value, a QNaNvalue, or ±infinity.XXXA source operand was too large to fit in thedestination format.XXXA result could not be represented exactly in thedestination format.CVTPS2PI69AMD64 TechnologyCVTSD2SI26568—Rev.
3.09—July 2007Convert Scalar Double-Precision Floating-Point toSigned Doubleword or Quadword IntegerConverts a scalar double-precision floating-point value in the low-order 64 bits of an XMM register ora 64-bit memory location to a 32-bit or 64-bit signed integer and writes the converted value in ageneral-purpose register.If the result of the conversion is an inexact value, the value is rounded as specified by the roundingcontrol bits (RC) in the MXCSR register.
If the floating-point value is a NaN, infinity, or if the result ofthe conversion is larger than the maximum signed doubleword (–231 to +231 – 1) or quadword value(–263 to +263 – 1), the instruction returns the indefinite integer value (8000_0000h for 32-bit integers,8000_0000_0000_0000h for 64-bit integers) when the invalid-operation exception (IE) is masked.The CVTSD2SI instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionCVTSD2SI reg32, xmm/mem64F2 0F 2D /rConverts a packed double-precision floating-point valuein an XMM register or 64-bit memory location to adoubleword integer in a general-purpose register.CVTSD2SI reg64, xmm/mem64F2 0F 2D /rConverts a packed double-precision floating-point valuein an XMM register or 64-bit memory location to aquadword integer in a general-purpose register.reg3231xmm2/mem64012764 630convertreg6463xmm2/mem64012764 630convertwith REX prefix70CVTSD2SIcvtsd2si.epsInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyRelated InstructionsCVTDQ2PD, CVTPD2DQ, CVTPD2PI, CVTPI2PD, CVTSI2SD, CVTTPD2DQ, CVTTPD2PI,CVTTSD2SIrFLAGS AffectedNoneMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEM1715141312111098765IEM43210Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFInstruction ReferenceXXCVTSD2SI71AMD64 TechnologyException26568—Rev.
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