Volume 4 128-Bit Media Instructions (794098), страница 13
Текст из файла (страница 13)
3.09—July 2007Convert Packed Double-Precision Floating-Point toPacked Doubleword IntegersConverts two packed double-precision floating-point values in an XMM register or a 128-bit memorylocation to two packed 32-bit signed integer values and writes the converted values in an MMXregister.If the result of the conversion is an inexact value, the value is rounded as specified by the roundingcontrol bits (RC) in the MXCSR register. If the floating-point value is a NaN, infinity, or if the result ofthe conversion is larger than the maximum signed doubleword (–231 to +231 – 1), the instructionreturns the 32-bit indefinite integer value (8000_0000h) when the invalid-operation exception (IE) ismasked.The CVTPD2PI instruction is an SSE2 instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTPD2PI mmx, xmm/mem128Description66 0F 2D /rConverts packed double-precision floating-pointvalues in an XMM register or 128-bit memory locationto packed doubleword integers values in thedestination MMX register.mmx6332 31xmm/mem128012764 63convert0convertcvtpd2pi.epsRelated InstructionsCVTDQ2PD, CVTPD2DQ, CVTPI2PD, CVTSD2SI, CVTSI2SD, CVTTPD2DQ, CVTTPD2PI,CVTTSD2SIrFLAGS AffectedNone54CVTPD2PIInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEM1715141312111098765IEM43210Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.General protection, #GPXx87 floating-pointexception pending, #MFXXXAn exception is pending due to an x87 floating-pointinstruction.SIMD Floating-PointException, #XFXXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.Instruction ReferenceCVTPD2PI55AMD64 TechnologyException26568—Rev.
3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Precision exception(PE)56XXXA source operand was an SNaN value, a QNaNvalue, or ±infinity.XXXA source operand was too large to fit in thedestination format.XXXA result could not be represented exactly in thedestination format.CVTPD2PIInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyCVTPD2PS Convert Packed Double-Precision Floating-Point toPacked Single-Precision Floating-PointConverts two packed double-precision floating-point values in an XMM register or a 128-bit memorylocation to two packed single-precision floating-point values and writes the converted values in thelow-order 64 bits of another XMM register.
The high-order 64 bits in the destination XMM register arecleared to all 0s.If the result of the conversion is an inexact value, the value is rounded as specified by the roundingcontrol bits (RC) in the MXCSR register.The CVTPD2PS instruction is an SSE2 instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTPD2PS xmm1,xmm2/mem128DescriptionConverts packed double-precision floating-pointvalues in an XMM register or 128-bit memorylocation to packed single-precision floating-pointvalues in the destination XMM register.66 0F 5A /rxmm112764 63xmm2/mem12832 31012764 6300convertconvertcvtpd2ps.epsRelated InstructionsCVTPS2PD, CVTSD2SS, CVTSS2SDrFLAGS AffectedNoneInstruction ReferenceCVTPD2PS57AMD64 Technology26568—Rev. 3.09—July 2007MXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEMMM543ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN value.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Underflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.58CVTPD2PSInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionDenormalized-operandexception (DE)XXXA source operand was a denormal value.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.Instruction ReferenceCVTPD2PS59AMD64 TechnologyCVTPI2PD26568—Rev. 3.09—July 2007Convert Packed Doubleword Integers to PackedDouble-Precision Floating-PointConverts two packed 32-bit signed integer values in an MMX register or a 64-bit memory location totwo double-precision floating-point values and writes the converted values in an XMM register.The CVTPI2PD instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeCVTPI2PD xmm, mmx/mem6466 0F 2A /rDescriptionConverts two packed doubleword integer values in anMMX register or 64-bit memory location to two packeddouble-precision floating-point values in the destinationXMM register.xmm12764 63mmx/mem6406332 310convertconvertcvtpi2pd.epsRelated InstructionsCVTDQ2PD, CVTPD2DQ, CVTPD2PI, CVTSD2SI, CVTSI2SD, CVTTPD2DQ, CVTTPD2PI,CVTTSD2SIrFLAGS AffectedNoneMXCSR Flags AffectedNone60CVTPI2PDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsRealVirtual8086ProtectedXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn exception was pending due to an x87 floatingpoint instruction.XXAn unaligned memory reference was performedwhile alignment checking was enabled.ExceptionInvalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXCause of ExceptionCVTPI2PD61AMD64 Technology26568—Rev.
3.09—July 2007CVTPI2PSConvert Packed Doubleword Integers toPacked Single-Precision Floating-PointConverts two packed 32-bit signed integer values in an MMX register or a 64-bit memory location totwo single-precision floating-point values and writes the converted values in the low-order 64 bits ofan XMM register. The high-order 64 bits of the XMM register are not modified.The CVTPI2PS instruction is an SSE instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTPI2PS xmm, mmx/mem640F 2A /rDescriptionConverts packed doubleword integer values in an MMXregister or 64-bit memory location to single-precisionfloating-point values in the destination XMM register.xmm12764 63mmx/mem6432 3106332 310convertconvertcvtpi2ps.epsRelated InstructionsCVTDQ2PS, CVTPS2DQ, CVTPS2PI, CVTSI2SS, CVTSS2SI, CVTTPS2DQ, CVTTPS2PI,CVTTSS2SIrFLAGS AffectedNone62CVTPI2PSInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEIE43210M1715141312111098765Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn exception was pending due to an x87 floatingpoint instruction.XXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFXAlignment check, #ACSIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsPrecision exception(PE)Instruction ReferenceXXXA result could not be represented exactly in thedestination format.CVTPI2PS63AMD64 TechnologyCVTPS2DQ26568—Rev.
3.09—July 2007Convert Packed Single-Precision Floating-Point toPacked Doubleword IntegersConverts four packed single-precision floating-point values in an XMM register or a 128-bit memorylocation to four packed 32-bit signed integer values and writes the converted values in another XMMregister.If the result of the conversion is an inexact value, the value is rounded as specified by the roundingcontrol bits (RC) in the MXCSR register. If the floating-point value is a NaN, infinity, or if the result ofthe conversion is larger than the maximum signed doubleword (–231 to +231 – 1), the instructionreturns the 32-bit indefinite integer value (8000_0000h) when the invalid-operation exception (IE) ismasked.The CVTPS2DQ instruction is an SSE2 instruction.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
