Volume 4 128-Bit Media Instructions (794098), страница 17
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Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM1.XXAn exception is pending due to an x87 floating-pointinstruction.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXx87 floating-pointexception pending, #MFSIMD Floating-PointException, #XF88XXXCVTTPD2PIInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Precision exception(PE)Instruction ReferenceXXXA source operand was an SNaN value, a QNaN value,or ±infinity.XXXA source operand was too large to fit in thedestination format.XXXA result could not be represented exactly in thedestination format.CVTTPD2PI89AMD64 TechnologyCVTTPS2DQ26568—Rev.
3.09—July 2007Convert Packed Single-Precision Floating-Pointto Packed Doubleword Integers, TruncatedConverts four packed single-precision floating-point values in an XMM register or a 128-bit memorylocation to four packed 32-bit signed integers and writes the converted values in another XMMregister.If the result of the conversion is an inexact value, the value is truncated (rounded toward zero). If thefloating-point value is a NaN, infinity, or if the result of the conversion is larger than the maximumsigned doubleword (–231 to +231 – 1), the instruction returns the 32-bit indefinite integer value(8000_0000h) when the invalid-operation exception (IE) is masked.The CVTTPS2DQ instruction is an SSE2 instruction. The presence of this instruction set is indicatedby a CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTTPS2DQ xmm1, xmm2/mem128DescriptionConverts packed single-precision floating-pointvalues in an XMM register or 128-bit memorylocation to packed doubleword integer values inthe destination XMM register.
Inexact results aretruncated.F3 0F 5B /rxmm112796 9564 63xmm2/mem12832 31012796 9564 6332 310convertconvertconvertconvertcvttps2dq.epsRelated InstructionsCVTDQ2PS, CVTPI2PS, CVTPS2DQ, CVTPS2PI, CVTSI2SS, CVTSS2SI, CVTTPS2PI,CVTTSS2SIrFLAGS AffectedNone90CVTTPS2DQInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEM1715141312111098765IEM43210Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Precision exception(PE)Instruction ReferenceXXXA source operand was an SNaN value, a QNaNvalue, or ±infinity.XXXA source operand was too large to fit in thedestination format.XXXA result could not be represented exactly in thedestination format.CVTTPS2DQ91AMD64 TechnologyCVTTPS2PI26568—Rev.
3.09—July 2007Convert Packed Single-Precision Floating-Pointto Packed Doubleword Integers, TruncatedConverts two packed single-precision floating-point values in the low-order 64 bits of an XMMregister or a 64-bit memory location to two packed 32-bit signed integer values and writes theconverted values in an MMX register.If the result of the conversion is an inexact value, the value is truncated (rounded toward zero).
If thefloating-point value is a NaN, infinity, or if the result of the conversion is larger than the maximumsigned doubleword (–231 to +231 – 1), the instruction returns the 32-bit indefinite integer value(8000_0000h) when the invalid-operation exception (IE) is masked.The CVTTPS2PI instruction is an SSE instruction. The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTTPS2PI mmx,xmm/mem640F 2C /rDescriptionConverts packed single-precision floating-point values inan XMM register or 64-bit memory location to doublewordinteger values in the destination MMX register. Inexactresults are truncated.mmx6332 31xmm/mem64012764 6332 31convert0convertcvttps2pi.epsRelated InstructionsCVTDQ2PS, CVTPI2PS, CVTPS2DQ, CVTPS2PI, CVTSI2SS, CVTSS2SI, CVTTPS2DQ,CVTTSS2SIrFLAGS AffectedNone92CVTTPS2PIInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEM1715141312111098765IEM43210Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn exception was pending due to an x87 floating-pointinstruction.XXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFXAlignment check, #ACSIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Precision exception(PE)Instruction ReferenceXXXA source operand was an SNaN value, a QNaN value,or ±infinity.XXXA source operand was too large to fit in thedestination format.XXXA result could not be represented exactly in thedestination format.CVTTPS2PI93AMD64 TechnologyCVTTSD2SI26568—Rev.
3.09—July 2007Convert Scalar Double-Precision Floating-Pointto Signed Doubleword of Quadword Integer,TruncatedConverts a double-precision floating-point value in the low-order 64 bits of an XMM register or a 64bit memory location to a 32-bit or 64-bit signed integer value and writes the converted value in ageneral-purpose register.If the result of the conversion is an inexact value, the value is truncated (rounded toward zero). If thefloating-point value is a NaN, infinity, or if the result of the conversion is larger than the maximumsigned doubleword (–231 to +231 – 1) or quadword value (–263 to +263 – 1), the instruction returns theindefinite integer value (8000_0000h for 32-bit integers, 8000_0000_0000_0000h for 64-bit integers)when the invalid-operation exception (IE) is masked.The CVTTSD2SI instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionCVTTSD2SI reg32,xmm/mem64F2 0F 2C /rConverts scalar double-precision floating-point value inan XMM register or 64-bit memory location to adoubleword signed integer value in a general-purposeregister. Inexact results are truncated.CVTTSD2SI reg64,xmm/mem64F2 0F 2C /rConverts scalar double-precision floating-point value inan XMM register or 64-bit memory location to aquadword signed integer value in a general-purposeregister. Inexact results are truncated.reg3231xmm2/mem64012764 630convertreg6463xmm2/mem64012764 630convertwith REX prefix94CVTTSD2SIcvttsd2si.epsInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyRelated InstructionsCVTDQ2PD, CVTPD2DQ, CVTPD2PI, CVTPI2PD, CVTSD2SI, CVTSI2SD, CVTTPD2DQ,CVTTPD2PIrFLAGS AffectedNoneMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEM1715141312111098765IEM43210Note: A flag that may be set to one or cleared to zero is M (modified).
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