Volume 4 128-Bit Media Instructions (794098), страница 18
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Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFInstruction ReferenceXXCVTTSD2SI95AMD64 TechnologyException26568—Rev.
3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Precision exception(PE)96XXXA source operand was an SNaN value, a QNaNvalue, or ±infinity.XXXA source operand was too large to fit in thedestination format.XXXA result could not be represented exactly in thedestination format.CVTTSD2SIInstruction Reference26568—Rev. 3.09—July 2007CVTTSS2SIAMD64 TechnologyConvert Scalar Single-Precision Floating-Point toSigned Doubleword or Quadword Integer,TruncatedConverts a single-precision floating-point value in the low-order 32 bits of an XMM register or a 32-bitmemory location to a 32-bit or 64-bit signed integer value and writes the converted value in a generalpurpose register.If the result of the conversion is an inexact value, the value is truncated (rounded toward zero).
If thefloating-point value is a NaN, infinity, or if the result of the conversion is larger than the maximumsigned doubleword (–231 to +231 – 1) or quadword value (–263 to +263 – 1), the instruction returns theindefinite integer value (8000_0000h for 32-bit integers, 8000_0000_0000_0000h for 64-bit integers)when the invalid-operation exception (IE) is masked.The CVTTSS2SI instruction is an SSE instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionCVTTSS2SI reg32,xmm/mem32F3 0F 2C /rConverts scalar single-precision floating-point value inan XMM register or 32-bit memory location to a signeddoubleword integer value in a general-purpose register.Inexact results are truncated.CVTTSS2SI reg64,xmm/mem32F3 0F 2C /rConverts scalar single-precision floating-point value inan XMM register or 32-bit memory location to a signedquadword integer value in a general-purpose register.Inexact results are truncated.reg3231xmm2/mem64012732 310convertreg6463xmm2/mem64012732 310convertwith REX prefixInstruction ReferenceCVTTSS2SIcvttss2si.eps97AMD64 Technology26568—Rev.
3.09—July 2007Related InstructionsCVTDQ2PS, CVTPI2PS, CVTPS2DQ, CVTPS2PI, CVTSI2SS, CVTSS2SI, CVTTPS2DQ,CVTTPS2PIrFLAGS AffectedNoneMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEM1715141312111098765IEM43210Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XF98XCVTTSS2SIInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Precision exception(PE)Instruction ReferenceXXXA source operand was an SNaN value, a QNaNvalue, or ±infinity.XXXA source operand was too large to fit in thedestination format.XXXA result could not be represented exactly in thedestination format.CVTTSS2SI99AMD64 TechnologyDIVPD26568—Rev.
3.09—July 2007Divide Packed Double-Precision Floating-PointDivides each of the two packed double-precision floating-point values in the first source operand bythe corresponding packed double-precision floating-point value in the second source operand andwrites the result of each division in the corresponding quadword of the destination (first source). Thefirst source/destination operand is an XMM register. The second source operand is another XMMregister or 128-bit memory location.The DIVPD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeDIVPD xmm1, xmm2/mem12866 0F 5E /rDescriptionDivides packed double-precision floating-point values inan XMM register by the packed double-precisionfloating-point values in another XMM register or 128-bitmemory location.xmm1127xmm2/mem12864 63012764 630dividedividedivpd.epsRelated InstructionsDIVPS, DIVSD, DIVSSrFLAGS AffectedNone100DIVPDInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEZEDEIEMMMMMM543210Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Overflow exception (OE)Instruction ReferenceXXXA source operand was an SNaN value.XXX±Zero was divided by ±zero.XXX±infinity was divided by ±infinity.XXXA rounded result was too large to fit into the format ofthe destination operand.DIVPD101AMD64 TechnologyException26568—Rev.
3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionUnderflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Zero-divide exception(ZE)XXXA non-zero number was divided by zero.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.102DIVPDInstruction Reference26568—Rev.
3.09—July 2007DIVPSAMD64 TechnologyDivide Packed Single-Precision Floating-PointDivides each of the four packed single-precision floating-point values in the first source operand by thecorresponding packed single-precision floating-point value in the second source operand and writesthe result of each division in the corresponding quadword of the destination (first source).
The firstsource/destination operand is an XMM register. The second source operand is another XMM registeror 128-bit memory location.The DIVPS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDIVPS xmm1, xmm/2mem1280F 5E /rDescriptionDivides packed single-precision floating-point values in anXMM register by the packed single-precision floating-pointvalues in another XMM register or 128-bit memorylocation.xmm112796 95xmm2/mem12864 6332 31012796 9564 6332 310dividedividedividedividedivps.epsRelated InstructionsDIVPD, DIVSD, DIVSSrFLAGS AffectedNoneInstruction ReferenceDIVPS103AMD64 Technology26568—Rev. 3.09—July 2007MXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEZEDEIEMMMMMM543210Note: A flag that may be set to one or cleared to zero is M (modified).
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