Volume 4 128-Bit Media Instructions (794098), страница 8
Текст из файла (страница 8)
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEMMM543ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsXXXA source operand was an SNaN value.XXX+infinity was added to –infinity.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Invalid-operationexception (IE)Instruction ReferenceADDSS13AMD64 TechnologyException26568—Rev.
3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionUnderflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.14ADDSSInstruction Reference26568—Rev. 3.09—July 2007ADDSUBPDAMD64 TechnologyAdd and Subtract Packed Double-PrecisionAdds the packed double-precision floating-point value in the high 64 bits of the source operand to thedouble-precision floating-point value in the high 64 bits of the destination operand and stores the sumin the high 64 bits of the destination operand; subtracts the packed double-precision floating-pointvalue in the low 64 bits of the source operand from the low 64 bits of the destination operand and storesthe difference in the low 64 bits of the destination operand.The ADDSUBPD instruction is an SSE3 instruction.
The presence of this instruction set is indicatedby a CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeADDSUBPD xmm1,xmm2/mem12866 0F D0 /rDescriptionAdds the value in the upper 64 bits of the sourceoperand to the value in the upper 64 bits of thedestination operand and stores the result in the upper64 bits of the destination operand; subtracts the value inthe lower 64 bits of the source operand from the value inthe lower 64 bits of the destination operand and storesthe result in the lower 64 bits of the destination operand.xmm1127xmm2/mem12864 63012764 630addsubRelated InstructionsADDSUBPSrFLAGS AffectedNoneInstruction ReferenceADDSUBPD15AMD64 Technology26568—Rev.
3.09—July 2007MXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEMMM543ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE3 instructions are not supported, asindicated by ECX bit 0 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCP was cleared to 0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions below for details.General protection, #GPXSIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsXXXA source operand was an SNaN value.XXX+infinity was added to –infinity.XXX+infinity was subtracted from +infinity.XXX–infinity was subtracted from –infinity.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Invalid-operationexception (IE)16ADDSUBPDInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionUnderflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.Instruction ReferenceADDSUBPD17AMD64 Technology26568—Rev. 3.09—July 2007ADDSUBPSAdd and Subtract Packed Single-PrecisionSubtracts the first and third single-precision floating-point values in the source operand from the firstand third single-precision floating-point values of the destination operand and stores the result in thefirst and third values of the destination operand.
Simultaneously, the instruction adds the second andfourth single-precision floating-point values in the source operand to the second and fourth singleprecision floating-point values in the destination operand and stores the result in the second and fourthvalues of the destination operand.The ADDSUBPS instruction is an SSE3 instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeADDSUBPS xmm1,xmm2/mem128DescriptionSubtracts the first and third packed single-precisionvalues in the source XMM register or 128-bit memoryoperand from the corresponding values in thedestination XMM register and stores the resultingvalues in the corresponding positions in the destinationregister; simultaneously, adds the second and fourthpacked single-precision values in the source XMMregister or 128-bit memory operand to thecorresponding values in the destination register andstores the result in the corresponding positions in thedestination register.F2 0F D0 /rxmm112796 9564 63xmm2/mem12832 31012796 9564 6332 310addsubaddsubRelated InstructionsADDSUBPDrFLAGS AffectedNone18ADDSUBPSInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UM11OM10ZMDM98IM7DAZ6PEUEOEMMM543ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE3 instructions are not supported, asindicated by ECX bit 0 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions below for details.General protection, #GPXSIMD Floating-PointException, #XFInstruction ReferenceXADDSUBPS19AMD64 TechnologyException26568—Rev.
3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionSIMD Floating-Point ExceptionsXXXA source operand was an SNaN value.XXX+infinity was added to –infinity.XXX+infinity was subtracted from +infinity.XXX–infinity was subtracted from –infinity.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Underflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.Invalid-operationexception (IE)20ADDSUBPSInstruction Reference26568—Rev.
3.09—July 2007ANDNPDAMD64 TechnologyLogical Bitwise AND NOTPacked Double-Precision Floating-PointPerforms a bitwise logical AND of the two packed double-precision floating-point values in thesecond source operand and the one’s-complement of the corresponding two packed double-precisionfloating-point values in the first source operand and writes the result in the destination (first source).The first source/destination operand is an XMM register. The second source operand is another XMMregister or 128-bit memory location.The ADDNPD instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeANDNPD xmm1, xmm2/mem12866 0F 55 /rDescriptionPerforms bitwise logical AND NOT of two packeddouble-precision floating-point values in an XMMregister and another XMM register or 128-bit memorylocation and writes the result in the destination XMMregister.xmm1127xmm2/mem12864 63invert012764 630invertANDANDandnpd.epsRelated InstructionsANDNPS, ANDPD, ANDPS, ORPD, ORPS, XORPD, XORPSrFLAGS AffectedNoneMXCSR Flags AffectedNoneInstruction ReferenceANDNPD21AMD64 Technology26568—Rev. 3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limit orwas non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MM wasset to 1.Invalid opcode, #UDGeneral protection,#GPX22ANDNPDInstruction Reference26568—Rev.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
