Volume 4 128-Bit Media Instructions (794098), страница 5
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The bias makes the range of the biased exponent always positive, which allows reciprocationwithout overflow.byteEight bits.clearTo write a bit value of 0. Compare set.compatibility modeA submode of long mode. In compatibility mode, the default address size is 32 bits, and legacy 16bit and 32-bit applications run without modification.commitTo irreversibly write, in program order, an instruction’s result to software-visible storage, such as aregister (including flags), the data cache, an internal write buffer, or memory.CPLCurrent privilege level.CR0–CR4A register range, from register CR0 through CR4, inclusive, with the low-order register first.CR0.PE = 1Notation indicating that the PE bit of the CR0 register has a value of 1.directReferencing a memory location whose address is included in the instruction’s syntax as animmediate operand.
The address may be an absolute or relative address. Compare indirect.PrefacexvAMD64 Technology26568—Rev. 3.09—July 2007dirty dataData held in the processor’s caches or internal buffers that is more recent than the copy held inmain memory.displacementA signed value that is added to the base of a segment (absolute addressing) or an instruction pointer(relative addressing).
Same as offset.doublewordTwo words, or four bytes, or 32 bits.double quadwordEight words, or 16 bytes, or 128 bits. Also called octword.DS:rSIThe contents of a memory location whose segment address is in the DS register and whose offsetrelative to that segment is in the rSI register.EFER.LME = 0Notation indicating that the LME bit of the EFER register has a value of 0.effective address sizeThe address size for the current instruction after accounting for the default address size and anyaddress-size override prefix.effective operand sizeThe operand size for the current instruction after accounting for the default operand size and anyoperand-size override prefix.elementSee vector.exceptionAn abnormal condition that occurs as the result of executing an instruction.
The processor’sresponse to an exception depends on the type of the exception. For all exceptions except 128-bitmedia SIMD floating-point exceptions and x87 floating-point exceptions, control is transferred tothe handler (or service routine) for that exception, as defined by the exception’s vector. Forfloating-point exceptions defined by the IEEE 754 standard, there are both masked and unmaskedresponses. When unmasked, the exception handler is called, and when masked, a default responseis provided instead of calling the handler.FF /0Notation indicating that FF is the first byte of an opcode, and a subopcode in the ModR/M byte hasa value of 0.xviPreface26568—Rev.
3.09—July 2007AMD64 TechnologyflushAn often ambiguous term meaning (1) writeback, if modified, and invalidate, as in “flush the cacheline,” or (2) invalidate, as in “flush the pipeline,” or (3) change a value, as in “flush to zero.”GDTGlobal descriptor table.GIFGlobal interrupt flag.IDTInterrupt descriptor table.IGNIgnore. Field is ignored.indirectReferencing a memory location whose address is in a register or other memory location. Theaddress may be an absolute or relative address. Compare direct.IRBThe virtual-8086 mode interrupt-redirection bitmap.ISTThe long-mode interrupt-stack table.IVTThe real-address mode interrupt-vector table.LDTLocal descriptor table.legacy x86The legacy x86 architecture.
See “Related Documents” on page xxiv for descriptions of the legacyx86 architecture.legacy modeAn operating mode of the AMD64 architecture in which existing 16-bit and 32-bit applications andoperating systems run without modification. A processor implementation of the AMD64architecture can run in either long mode or legacy mode.
Legacy mode has three submodes, realmode, protected mode, and virtual-8086 mode.long modeAn operating mode unique to the AMD64 architecture. A processor implementation of theAMD64 architecture can run in either long mode or legacy mode. Long mode has two submodes,64-bit mode and compatibility mode.PrefacexviiAMD64 Technology26568—Rev. 3.09—July 2007lsbLeast-significant bit.LSBLeast-significant byte.main memoryPhysical memory, such as RAM and ROM (but not cache memory) that is installed in a particularcomputer system.mask(1) A control bit that prevents the occurrence of a floating-point exception from invoking anexception-handling routine.
(2) A field of bits used for a control purpose.MBZMust be zero. If software attempts to set an MBZ bit to 1, a general-protection exception (#GP)occurs.memoryUnless otherwise specified, main memory.ModRMA byte following an instruction opcode that specifies address calculation based on mode (Mod),register (R), and memory (M) variables.moffsetA 16, 32, or 64-bit offset that specifies a memory operand directly, without using a ModRM or SIBbyte.msbMost-significant bit.MSBMost-significant byte.multimedia instructionsA combination of 128-bit media instructions and 64-bit media instructions.octwordSame as double quadword.offsetSame as displacement.xviiiPreface26568—Rev. 3.09—July 2007AMD64 TechnologyoverflowThe condition in which a floating-point number is larger in magnitude than the largest, finite,positive or negative number that can be represented in the data-type format being used.packedSee vector.PAEPhysical-address extensions.physical memoryActual memory, consisting of main memory and cache.probeA check for an address in a processor’s caches or internal buffers.
External probes originateoutside the processor, and internal probes originate within the processor.protected modeA submode of legacy mode.quadwordFour words, or eight bytes, or 64 bits.RAZRead as zero (0), regardless of what is written.real-address modeSee real mode.real modeA short name for real-address mode, a submode of legacy mode.relativeReferencing with a displacement (also called offset) from an instruction pointer rather than thebase of a code segment. Contrast with absolute.reservedFields marked as reserved may be used at some future time.To preserve compatibility with future processors, reserved fields require special handling whenread or written by software.Reserved fields may be further qualified as MBZ, RAZ, SBZ or IGN (see definitions).Software must not depend on the state of a reserved field, nor upon the ability of such fields toreturn to a previously written state.If a reserved field is not marked with one of the above qualifiers, software must not change the stateof that field; it must reload that field with the same values returned from a prior read.PrefacexixAMD64 Technology26568—Rev.
3.09—July 2007REXAn instruction prefix that specifies a 64-bit operand size and provides access to additionalregisters.RIP-relative addressingAddressing relative to the 64-bit RIP instruction pointer.setTo write a bit value of 1. Compare clear.SIBA byte following an instruction opcode that specifies address calculation based on scale (S), index(I), and base (B).SIMDSingle instruction, multiple data. See vector.SSEStreaming SIMD extensions instruction set.
See 128-bit media instructions and 64-bit mediainstructions.SSE2Extensions to the SSE instruction set. See 128-bit media instructions and 64-bit mediainstructions.SSE3Further extensions to the SSE instruction set. See 128-bit media instructions.sticky bitA bit that is set or cleared by hardware and that remains in that state until explicitly changed bysoftware.TOPThe x87 top-of-stack pointer.TSSTask-state segment.underflowThe condition in which a floating-point number is smaller in magnitude than the smallest nonzero,positive or negative number that can be represented in the data-type format being used.vector(1) A set of integer or floating-point values, called elements, that are packed into a single operand.Most of the 128-bit and 64-bit media instructions use vectors as operands.
Vectors are also calledpacked or SIMD (single-instruction multiple-data) operands.xxPreface26568—Rev. 3.09—July 2007AMD64 Technology(2) An index into an interrupt descriptor table (IDT), used to access exception handlers. Compareexception.virtual-8086 modeA submode of legacy mode.VMCBVirtual machine control block.VMMVirtual machine monitor.wordTwo bytes, or 16 bits.x86See legacy x86.RegistersIn the following list of registers, the names are used to refer either to a given register or to the contentsof that register:AH–DHThe high 8-bit AH, BH, CH, and DH registers. Compare AL–DL.AL–DLThe low 8-bit AL, BL, CL, and DL registers.
Compare AH–DH.AL–r15BThe low 8-bit AL, BL, CL, DL, SIL, DIL, BPL, SPL, and R8B–R15B registers, available in 64-bitmode.BPBase pointer register.CRnControl register number n.CSCode segment register.eAX–eSPThe 16-bit AX, BX, CX, DX, DI, SI, BP, and SP registers or the 32-bit EAX, EBX, ECX, EDX,EDI, ESI, EBP, and ESP registers.
Compare rAX–rSP.PrefacexxiAMD64 Technology26568—Rev. 3.09—July 2007EFERExtended features enable register.eFLAGS16-bit or 32-bit flags register. Compare rFLAGS.EFLAGS32-bit (extended) flags register.eIP16-bit or 32-bit instruction-pointer register. Compare rIP.EIP32-bit (extended) instruction-pointer register.FLAGS16-bit flags register.GDTRGlobal descriptor table register.GPRsGeneral-purpose registers. For the 16-bit data size, these are AX, BX, CX, DX, DI, SI, BP, and SP.For the 32-bit data size, these are EAX, EBX, ECX, EDX, EDI, ESI, EBP, and ESP.
For the 64-bitdata size, these include RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, and R8–R15.IDTRInterrupt descriptor table register.IP16-bit instruction-pointer register.LDTRLocal descriptor table register.MSRModel-specific register.r8–r15The 8-bit R8B–R15B registers, or the 16-bit R8W–R15W registers, or the 32-bit R8D–R15Dregisters, or the 64-bit R8–R15 registers.rAX–rSPThe 16-bit AX, BX, CX, DX, DI, SI, BP, and SP registers, or the 32-bit EAX, EBX, ECX, EDX,EDI, ESI, EBP, and ESP registers, or the 64-bit RAX, RBX, RCX, RDX, RDI, RSI, RBP, and RSPxxiiPreface26568—Rev.
3.09—July 2007AMD64 Technologyregisters. Replace the placeholder r with nothing for 16-bit size, “E” for 32-bit size, or “R” for 64bit size.RAX64-bit version of the EAX register.RBP64-bit version of the EBP register.RBX64-bit version of the EBX register.RCX64-bit version of the ECX register.RDI64-bit version of the EDI register.RDX64-bit version of the EDX register.rFLAGS16-bit, 32-bit, or 64-bit flags register.
Compare RFLAGS.RFLAGS64-bit flags register. Compare rFLAGS.rIP16-bit, 32-bit, or 64-bit instruction-pointer register. Compare RIP.RIP64-bit instruction-pointer register.RSI64-bit version of the ESI register.RSP64-bit version of the ESP register.SPStack pointer register.SSStack segment register.PrefacexxiiiAMD64 Technology26568—Rev.
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