Volume 4 128-Bit Media Instructions (794098), страница 4
Текст из файла (страница 4)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361RCPPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363RCPSS . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365RSQRTPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367RSQRTSS . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369SHUFPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371SHUFPS. . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373SQRTPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376SQRTPS . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378SQRTSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380SQRTSS . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382STMXCSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384SUBPD .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385SUBPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 388SUBSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391SUBSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394ivContents26568—Rev. 3.09—July 2007AMD64 TechnologyUCOMISD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 397UCOMISS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400UNPCKHPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 403UNPCKHPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405UNPCKLPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 407UNPCKLPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409XORPD . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411XORPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413Index . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415ContentsvAMD64 Technologyvi26568—Rev. 3.09—July 2007Contents26568—Rev. 3.09—July 2007AMD64 TechnologyFiguresFigure 1-1.FiguresDiagram Conventions for 128-Bit Media Instructions . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1viiAMD64 Technologyviii26568—Rev. 3.09—July 2007Figures26568—Rev. 3.09—July 2007AMD64 TechnologyTablesTable 1-1.Immediate Operand Values for Comparison Operations . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 31Table 1-2.Immediate-Byte Operand Encoding for 128-Bit PEXTRW . . . . . . . . . . . . . . . . . . . . . . . . . . . 272Table 1-3.Immediate-Byte Operand Encoding for 128-Bit PINSRW. . . . . . . . . . . . . . . . . . . . . . . . . . . . 274Table 1-4.Immediate-Byte Operand Encoding for PSHUFD . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301Table 1-5.Immediate-Byte Operand Encoding for PSHUFHW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304Table 1-6.Immediate-Byte Operand Encoding for PSHUFLW . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 307Table 1-7.Immediate-Byte Operand Encoding for SHUFPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371Table 1-8.Immediate-Byte Operand Encoding for SHUFPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373TablesixAMD64 Technologyx26568—Rev. 3.09—July 2007Tables26568—Rev. 3.09—July 2007AMD64 TechnologyRevision HistoryDateRevisionDescriptionJuly 20073.09Added the following instructions: EXTRQ on page 112, INSERTQ onpage 130, MOVNTSD on page 192, and MOVNTSS on page 194.Added misaligned exception mask (MXCSR.MM) information.Added imm8 values with corresponding mnemonics to CMPPD on page 29,CMPPS on page 33, CMPSD on page 36, and CMPSS on page 39.Reworded CPUID information in condition tables.Added minor clarifications and corrected typographical and formattingerrors.September20063.08Made minor corrections.December20053.07Made minor editorial and formatting changes.January 20053.06Added documentation on SSE3 instructions.
Corrected numerous minorfactual errors and typos.September20033.05Made numerous small factual corrections.April 20033.04Made minor corrections.Revision HistoryxiAMD64 Technologyxii26568—Rev. 3.09—July 2007Revision History26568—Rev. 3.09—July 2007AMD64 TechnologyPrefaceAbout This BookThis book is part of a multivolume work entitled the AMD64 Architecture Programmer’s Manual.
Thistable lists each volume and its order number.TitleOrder No.Volume 1: Application Programming24592Volume 2: System Programming24593Volume 3: General-Purpose and System Instructions24594Volume 4: 128-Bit Media Instructions26568Volume 5: 64-Bit Media and x87 Floating-Point Instructions26569AudienceThis volume (Volume 4) is intended for all programmers writing application or system software forprocessors that implement the AMD64 architecture.Contact InformationTo submit questions or comments concerning this document, contact our technical documentation staffat AMD64.Feedback@amd.com.OrganizationVolumes 3, 4, and 5 describe the AMD64 architecture’s instruction set in detail. Together, they covereach instruction’s mnemonic syntax, opcodes, functions, affected flags, and possible exceptions.The AMD64 instruction set is divided into five subsets:•••••General-purpose instructionsSystem instructions128-bit media instructions64-bit media instructionsx87 floating-point instructionsSeveral instructions belong to—and are described identically in—multiple instruction subsets.PrefacexiiiAMD64 Technology26568—Rev.
3.09—July 2007This volume describes the 128-bit media instructions. The index at the end cross-references topicswithin this volume. For other topics relating to the AMD64 architecture, and for information oninstructions in other subsets, see the tables of contents and indexes of the other volumes.DefinitionsMany of the following definitions assume an in-depth knowledge of the legacy x86 architecture. See“Related Documents” on page xxiv for descriptions of the legacy x86 architecture.Terms and NotationIn addition to the notation described below, “Opcode-Syntax Notation” in Volume 3 describes notationrelating specifically to opcodes.1011bA binary value—in this example, a 4-bit value.F0EAhA hexadecimal value—in this example a 2-byte value.[1,2)A range that includes the left-most value (in this case, 1) but excludes the right-most value (in thiscase, 2).7–4A bit range, from bit 7 to 4, inclusive.
The high-order bit is shown first.128-bit media instructionsInstructions that use the 128-bit XMM registers. These are a combination of the SSE, SSE2 andSSE3 instruction sets.64-bit media instructionsInstructions that use the 64-bit MMX registers. These are primarily a combination of MMX™ and3DNow!™ instruction sets, with some additional instructions from the SSE and SSE2 instructionsets.16-bit modeLegacy mode or compatibility mode in which a 16-bit address size is active.
See legacy mode andcompatibility mode.32-bit modeLegacy mode or compatibility mode in which a 32-bit address size is active. See legacy mode andcompatibility mode.xivPreface26568—Rev. 3.09—July 2007AMD64 Technology64-bit modeA submode of long mode. In 64-bit mode, the default address size is 64 bits and new features, suchas register extensions, are supported for system and application software.#GP(0)Notation indicating a general-protection exception (#GP) with error code of 0.absoluteSaid of a displacement that references the base of a code segment rather than an instruction pointer.Contrast with relative.ASIDAddress space identifier.biased exponentThe sum of a floating-point value’s exponent and a constant bias for a particular floating-point datatype.
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