Volume 4 128-Bit Media Instructions (794098), страница 10
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3.09—July 2007Table 1-1.AMD64 TechnologyImmediate Operand Values for Comparison OperationsResult If NaN OperandQNaN Operand CausesInvalid OperationExceptionEqualFALSENoLess thanFALSEYesGreater than(uses swapped operands)FALSEYesLess than or equalFALSEYes010Greater than or equal(uses swapped operands)FALSEYes011UnorderedTRUENo100Not equalTRUENoNot less thanTRUEYesNot greater than(uses swapped operands)TRUEYesNot less than or equalTRUEYes110Not greater than or equal(uses swapped operands)TRUEYes111OrderedFALSENoImmediate-Byte Value(bits 2–0)000001101Compare OperationRelated InstructionsCMPPS, CMPSD, CMPSS, COMISD, COMISS, UCOMISD, UCOMISSrFLAGS AffectedNoneMXCSR Flags AffectedMM17FZ15RC14PM1312UM11OM10ZM9DM8IM7DAZ6PE5UE4OE3ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified).
Unaffected flags are blank.Instruction ReferenceCMPPD31AMD64 Technology26568—Rev. 3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-point exceptionwhile CR4.OSXMMEXCPT was cleared to 0.See SIMD Floating-Point Exceptions, below, for details.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limit orwas non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MM wasset to 1.XXThere was an unmasked SIMD floating-point exceptionwhile CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, for details.Invalid opcode, #UDGeneral protection,#GPXSIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Denormalizedoperand exception(DE)32XXXA source operand was an SNaN value.XXXA source operand was a QNaN value, and thecomparison does not allow QNaN values (refer toTable 1-1 on page 31).XXXA source operand was a denormal value.CMPPDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyCMPPSCompare Packed Single-PrecisionFloating-PointCompares each of the four packed single-precision floating-point values in the first source operandwith the corresponding packed single-precision floating-point value in the second source operand andwrites the result of each comparison in the corresponding 32 bits of the destination (first source). Thetype of comparison is specified by the three low-order bits of the immediate-byte operand, as shown inTable 1-1 on page 31. The result of each compare is a 32-bit value of all 1s (TRUE) or all 0s (FALSE).The first source/destination operand is an XMM register. The second source operand is another XMMregister or 128-bit memory location.Signed compares return TRUE only if both operands are valid numbers, and the numbers have therelation specified by the type of compare.
"Ordered" compare returns TRUE if both operands are validnumbers, or FALSE if either operand is a NaN. "Unordered" compare returns TRUE only if one orboth operands are NaN, and FALSE otherwise.QNaN operands generate an Invalid Operation Exception only if the compare type isn't "Equal","Unequal", "Ordered", or "Unordered". SNaN operands always generate an Invalid OperationException (IE).Some comparison operations that are not directly supported by the immediate-byte encodings can beimplemented by swapping the contents of the source and destination operands and then executing theappropriate compare instruction using the swapped values. These additional comparison operationsare shown in Table 1-1 on page 31.
When swapping operands, the first source XMM register isoverwritten by the result.The CMPPS instruction with appropriate value of imm8 is aliased to the following mnemonics tofacilitate coding with this instruction.MnemonicInstruction ReferenceImplied Value ofimm8CMPEQPS0CMPLTPS1CMPLEPS2CMPUNORDPS3CMPNEQPS4CMPNLTPS5CMPNLEPS6CMPORDPS7CMPPS33AMD64 Technology26568—Rev. 3.09—July 2007The CMPPS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeCMPPS xmm1, xmm2/mem128, imm8DescriptionCompares four pairs of packed singleprecision floating-point values in an XMMregister and an XMM register or 64-bitmemory location.0F C2 /r ibxmm1.12796 95xmm2/mem128.64 63.32 31.0127imm896 9564 6332 31.0.7 0comparecompareall 1s or 0sall 1s or 0scmpps.epsRelated InstructionsCMPPD, CMPSD, CMPSS, COMISD, COMISS, UCOMISD, UCOMISSrFLAGS AffectedNone34CMPPSInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZPE65UE4OEZE32DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified).
Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsXXXA source operand was an SNaN value.Invalid-operationexception (IE)XXXA source operand was a QNaN value, and thecomparison does not allow QNaN values (refer toTable 1-1 on page 31).Denormalized-operandexception (DE)XXXA source operand was a denormal value.Instruction ReferenceCMPPS35AMD64 Technology26568—Rev.
3.09—July 2007CMPSDCompare Scalar Double-PrecisionFloating-PointCompares the double-precision floating-point value in the low-order 64 bits of the first source operandwith the double-precision floating-point value in the low-order 64 bits of the second source operandand writes the result in the low-order 64 bits of the destination (first source). The type of comparison isspecified by the three low-order bits of the immediate-byte operand, as shown in Table 1-1 on page 31.The result of the compare is a 64-bit value of all 1s (TRUE) or all 0s (FALSE). The firstsource/destination operand is an XMM register. The second source operand is another XMM registeror 64-bit memory location.
The high-order 64 bits of the destination XMM register are not modified.Signed compares return TRUE only if both operands are valid numbers, and the numbers have therelation specified by the type of compare. "Ordered" compare returns TRUE if both operands are validnumbers, or FALSE if either operand is a NaN. "Unordered" compare returns TRUE only if one orboth operands are NaN, and FALSE otherwise.QNaN operands generate an Invalid Operation Exception only if the compare type isn't "Equal","Unequal", "Ordered", or "Unordered". SNaN operands always generate an Invalid OperationException (IE).Some comparison operations that are not directly supported by the immediate-byte encodings can beimplemented by swapping the contents of the source and destination operands and then executing theappropriate compare instruction using the swapped values.
These additional comparison operationsare shown in Table 1-1 on page 31. When swapping operands, the first source XMM register isoverwritten by the result.The CMPSD instruction with appropriate value of imm8 is aliased to the following mnemonics tofacilitate coding with this instruction.Mnemonic36Implied Value ofimm8CMPEQSD0CMPLTSD1CMPLESD2CMPUNORDSD3CMPNEQSD4CMPNLTSD5CMPNLESD6CMPORDSD7CMPSDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyThis CMPSD instruction should not be confused with the same-mnemonic CMPSD (compare stringsby doubleword) instruction in the general-purpose instruction set. Assemblers can distinguish theinstructions by the number and type of operands.The CMPSD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCMPSD xmm1, xmm2/mem64, imm8DescriptionCompares double-precision floating-pointvalues in an XMM register and an XMMregister or 64-bit memory location.F2 0F C2 /r ibxmm112764 63xmm2/mem64012764 630imm87 0compareall 1s or 0scmpsd.epsRelated InstructionsCMPPD, CMPPS, CMPSS, COMISD, COMISS, UCOMISD, UCOMISSrFLAGS AffectedNoneInstruction ReferenceCMPSD37AMD64 Technology26568—Rev. 3.09—July 2007MXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZPE65UE4OEZE32DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified).
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