Volume 4 128-Bit Media Instructions (794098), страница 23
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For data that is shared bymultiple processors, this instruction should be used together with a fence instruction in order to ensuredata coherency (refer to “Cache and TLB Management” in Volume 2).The MASKMOVDQU instruction is an SSE2 instruction. The presence of this instruction set isindicated by a CPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeMASKMOVDQU xmm1, xmm2DescriptionStore bytes from an XMM register selected by a maskvalue in another XMM register to DS:rDI.66 0F F7 /rxmm2xmm11270............................1270..............selectselectstore addressMemory136DS:rDImaskmovdqu.epsMASKMOVDQUInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyRelated InstructionsMASKMOVQrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.General protection,#GPXXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XA page fault resulted from the execution of theinstruction.Invalid opcode, #UDPage fault, #PFInstruction ReferenceXMASKMOVDQU137AMD64 TechnologyMAXPD26568—Rev.
3.09—July 2007Maximum Packed Double-Precision Floating-PointCompares each of the two packed double-precision floating-point values in the first source operandwith the corresponding packed double-precision floating-point value in the second source operand andwrites the numerically greater of the two values for each comparison in the corresponding quadword ofthe destination (first source). The first source/destination operand is an XMM register. The secondsource operand is another XMM register or 128-bit memory location.If both source operands are equal to zero, the value in the second source operand is returned. If eitheroperand is a NaN (SNaN or QNaN), and invalid-operation exceptions are masked, the second sourceoperand is written to the destination.The MAXPD instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeMAXPD xmm1, xmm2/mem12866 0F 5F /rDescriptionCompares two pairs of packed double-precision valuesin an XMM register and another XMM register or 128-bitmemory location and writes the greater value of eachcomparison in the destination XMM register.xmm1127xmm2/mem12864 63012764 630maximummaximummaxpd.epsRelated InstructionsMAXPS, MAXSD, MAXSS, MINPD, MINPS, MINSD, MINSSrFLAGS AffectedNone138MAXPDInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZPE65UE4OEZE32DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified).
Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN or QNaN value.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Instruction ReferenceMAXPD139AMD64 TechnologyMAXPS26568—Rev.
3.09—July 2007Maximum Packed Single-Precision Floating-PointCompares each of the four packed single-precision floating-point values in the first source operandwith the corresponding packed single-precision floating-point value in the second source operand andwrites the numerically greater of the two values for each comparison in the corresponding doublewordof the destination (first source). The first source/destination operand is an XMM register. The secondsource operand is another XMM register or 128-bit memory location.If both source operands are equal to zero, the value in the second source operand is returned. If eitheroperand is a NaN (SNaN or QNaN), and invalid-operation exceptions are masked, the second sourceoperand is written to the destination.The MAXPS instruction is an SSE instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeMAXPS xmm1, xmm2/mem128DescriptionCompares four pairs of packed single-precision values in anXMM register and another XMM register or 128-bit memorylocation and writes the maximum value of each comparisonin the destination XMM register.0F 5F /rxmm112796 9564 63xmm2/mem12832 31012796 9564 6332 310maximummaximummaximummaximummaxps.epsRelated InstructionsMAXPD, MAXSD, MAXSS, MINPD, MINPS, MINSD, MINSSrFLAGS AffectedNone140MAXPSInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZPE65UE4OEZE32DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified).
Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions for details.General protection, #GPXSIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN or QNaN value.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Instruction ReferenceMAXPS141AMD64 TechnologyMAXSD26568—Rev.
3.09—July 2007Maximum Scalar Double-Precision Floating-PointCompares the double-precision floating-point value in the low-order 64 bits of the first source operandwith the double-precision floating-point value in the low-order 64 bits of the second source operandand writes the numerically greater of the two values in the low-order quadword of the destination (firstsource). The first source/destination operand is an XMM register. The second source operand isanother XMM register or a 64-bit memory location. The high-order quadword of the destination XMMregister is not modified.If both source operands are equal to zero, the value in the second source operand is returned.
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