Volume 4 128-Bit Media Instructions (794098), страница 27
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3.09—July 2007MOVHLPSMove Packed Single-Precision Floating-PointHigh to LowMoves two packed single-precision floating-point values from the high-order 64 bits of an XMMregister to the low-order 64 bits of another XMM register. The high-order 64 bits of the destinationXMM register are not modified.The MOVHLPS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeMOVHLPS xmm1, xmm2DescriptionMoves two packed single-precision floating-point values froman XMM register to the destination XMM register.0F 12 /rxmm112764 63xmm232 31012796 95copy64 630copymovhlps.epsRelated InstructionsMOVAPS, MOVHPS, MOVLHPS, MOVLPS, MOVMSKPS, MOVSS, MOVUPSrFLAGS AffectedNoneMXCSR Flags AffectedNone170MOVHLPSInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyExceptionsExceptionInvalid opcode, #UDDevice not available,#NMInstruction ReferenceRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.XXXThe task-switch bit (TS) of CR0 was set to 1.MOVHLPS171AMD64 Technology26568—Rev.
3.09—July 2007MOVHPDMove High Packed Double-PrecisionFloating-PointMoves a double-precision floating-point value:••from a 64-bit memory location to the high-order 64 bits of an XMM register, orfrom the high-order 64 bits of an XMM register to a 64-bit memory location.The low-order 64 bits of the destination XMM register are not modified.The MOVHPD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionMOVHPD xmm, mem6466 0F 16 /rMoves double-precision floating-point value from a 64-bitmemory location to an XMM register.MOVHPD mem64, xmm66 0F 17 /rMoves double-precision floating-point value from an XMMregister to a 64-bit memory location.xmm127mem6464 630630copymem6463xmm012732 310copymovhpd.epsRelated InstructionsMOVAPD, MOVLPD, MOVMSKPD, MOVSD, MOVUPDrFLAGS AffectedNone172MOVHPDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001hXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.Invalid opcode, #UDGeneral protection,#GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceMOVHPD173AMD64 TechnologyMOVHPS26568—Rev.
3.09—July 2007Move High Packed Single-Precision Floating-PointMoves two packed single-precision floating-point values:••from a 64-bit memory location to the high-order 64 bits of an XMM register, orfrom the high-order 64 bits of an XMM register to a 64-bit memory location.The low-order 64 bits of the destination XMM register are not modified.The MOVHPS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionMOVHPS xmm, mem640F 16 /rMoves two packed single-precision floating-point values from a64-bit memory location to an XMM register.MOVHPS mem64, xmm0F 17 /rMoves two packed single-precision floating-point values from anXMM register to a 64-bit memory location.xmm12796 95mem6464 6306332 31copymem646332 310copyxmm012796 95copy64 630copymovhps.epsRelated InstructionsMOVAPS, MOVHLPS, MOVLHPS, MOVLPS, MOVMSKPS, MOVSS, MOVUPSrFLAGS AffectedNone174MOVHPSInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.Invalid opcode, #UDGeneral protection,#GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceMOVHPS175AMD64 Technology26568—Rev.
3.09—July 2007MOVLHPSMove Packed Single-Precision Floating-PointLow to HighMoves two packed single-precision floating-point values from the low-order 64 bits of an XMMregister to the high-order 64 bits of another XMM register. The low-order 64 bits of the destinationXMM register are not modified.The MOVLHPS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeMOVLHPS xmm1, xmm20F 16 /rDescriptionMoves two packed single-precision floating-point values from anXMM register to another XMM register.xmm112796 9564 63xmm2012764 6332 31copy0copymovlhps.epsRelated InstructionsMOVAPS, MOVHLPS, MOVHPS, MOVLPS, MOVMSKPS, MOVSS, MOVUPSrFLAGS AffectedNoneMXCSR Flags AffectedNone176MOVLHPSInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyExceptionsExceptionInvalid opcode, #UDDevice not available,#NMInstruction ReferenceRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.XXXThe task-switch bit (TS) of CR0 was set to 1.MOVLHPS177AMD64 Technology26568—Rev.
3.09—July 2007MOVLPDMove Low Packed Double-PrecisionFloating-PointMoves a double-precision floating-point value:••from a 64-bit memory location to the low-order 64 bits of an XMM register, orfrom the low-order 64 bits of an XMM register to a 64-bit memory location.The high-order 64 bits of the destination XMM register are not modified.The MOVLPD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionMOVLPD xmm, mem6466 0F 12 /rMoves double-precision floating-point value from a 64-bitmemory location to an XMM register.MOVLPD mem64, xmm66 0F 13 /rMoves double-precision floating-point value from an XMMregister to a 64-bit memory location.xmm127mem6464 630630copymem6463xmm012764 630copymovlpd.epsRelated InstructionsMOVAPD, MOVHPD, MOVMSKPD, MOVSD, MOVUPDrFLAGS AffectedNone178MOVLPDInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.Invalid opcode, #UDGeneral protection,#GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceMOVLPD179AMD64 Technology26568—Rev.
3.09—July 2007MOVLPSMove Low Packed Single-PrecisionFloating-PointMoves two packed single-precision floating-point values:••from a 64-bit memory location to the low-order 64 bits of an XMM register, orfrom the low-order 64 bits of an XMM register to a 64-bit memory locationThe high-order 64 bits of the destination XMM register are not modified.The MOVLPS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionMOVLPS xmm, mem640F 12 /rMoves two packed single-precision floating-point values from a64-bit memory location to an XMM register.MOVLPS mem64, xmm0F 13 /rMoves two packed single-precision floating-point values from anXMM register to a 64-bit memory location.xmm12764 63mem6432 3106332 31copymem646332 310copyxmm012764 6332 31copy0copymovlps.epsRelated InstructionsMOVAPS, MOVHLPS, MOVHPS, MOVLHPS, MOVMSKPS, MOVSS, MOVUPS180MOVLPSInstruction Reference26568—Rev.
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