Volume 4 128-Bit Media Instructions (794098), страница 31
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3.09—July 2007xmm112796 9564 63xmm2/mem12832 31012796 9564 6332 310copycopycopycopyxmm1/mem12812796 9564 63xmm232 31012796 9564 6332 310copycopycopycopymovups.epsRelated InstructionsMOVAPS, MOVHLPS, MOVHPS, MOVLHPS, MOVLPS, MOVMSKPS, MOVSSrFLAGS AffectedNoneMXCSR Flags AffectedNone212MOVUPSInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.Invalid opcode, #UDGeneral protection,#GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceMOVUPS213AMD64 TechnologyMULPD26568—Rev.
3.09—July 2007Multiply Packed Double-Precision Floating-PointMultiplies each of the two packed double-precision floating-point values in the first source operand bythe corresponding packed double-precision floating-point value in the second source operand andwrites the result of each multiplication operation in the corresponding quadword of the destination(first source). The first source/destination operand is an XMM register.
The second source operand isanother XMM register or 128-bit memory location.The MULPD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeMULPD xmm1, xmm2/mem12866 0F 59 /rDescriptionMultiplies packed double-precision floating-point valuesin an XMM register and another XMM register or 128-bitmemory location and writes the results in the destinationXMM register.xmm1127xmm2/mem12864 63012764 630multiplymultiplymulpd.epsRelated InstructionsMULPS, MULSD, MULSS, PFMULrFLAGS AffectedNone214MULPDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEMMM543ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN value.XXX±Zero was multiplied by ±infinity.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Underflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.Instruction ReferenceMULPD215AMD64 TechnologyException26568—Rev.
3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionDenormalized-operandexception (DE)XXXA source operand was a denormal value.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.216MULPDInstruction Reference26568—Rev.
3.09—July 2007MULPSAMD64 TechnologyMultiply Packed Single-Precision Floating-PointMultiplies each of the four packed single-precision floating-point values in first source operand by thecorresponding packed single-precision floating-point value in the second source operand and writesthe result of each multiplication operation in the corresponding doubleword of the destination (firstsource). The first source/destination operand is an XMM register. The second source operand isanother XMM register or 128-bit memory location.The MULPS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeMULPS xmm1, xmm2/mem1280F 59 /rDescriptionMultiplies packed single-precision floating-point values inan XMM register and another XMM register or 128-bitmemory location and writes the results in the destinationXMM register.xmm112796 95xmm2/mem12864 6332 31012796 9564 6332 310multiplymultiplymultiplymultiplymulps.epsRelated InstructionsMULPD, MULSD, MULSS, PFMULrFLAGS AffectedNoneInstruction ReferenceMULPS217AMD64 Technology26568—Rev. 3.09—July 2007MXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEMMM543ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified).
Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN value.XXX±Zero was multiplied by ±infinity.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Underflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.218MULPSInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionDenormalized-operandexception (DE)XXXA source operand was a denormal value.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.Instruction ReferenceMULPS219AMD64 TechnologyMULSD26568—Rev.
3.09—July 2007Multiply Scalar Double-Precision Floating-PointMultiplies the double-precision floating-point value in the low-order quadword of first source operandby the double-precision floating-point value in the low-order quadword of the second source operandand writes the result in the low-order quadword of the destination (first source). The high-orderquadword of the destination is not modified. The first source/destination operand is an XMM register.The second source operand is another XMM register or 64-bit memory location.The MULSD instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeMULSD xmm1, xmm2/mem64F2 0F 59 /rDescriptionMultiplies low-order double-precision floating-point valuesin an XMM register and another XMM register or 64-bitmemory location and writes the result in the low-orderquadword of the destination XMM register.xmm1127xmm2/mem6464 63012764 630multiplymulsd.epsRelated InstructionsMULPD, MULPS, MULSS, PFMULrFLAGS AffectedNone220MULSDInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEMMM543ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified).
Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN value.XXX±Zero was multiplied by ±infinity.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Underflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.Instruction ReferenceMULSD221AMD64 TechnologyException26568—Rev.
3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionDenormalized-operandexception (DE)XXXA source operand was a denormal value.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.222MULSDInstruction Reference26568—Rev. 3.09—July 2007MULSSAMD64 TechnologyMultiply Scalar Single-Precision Floating-PointMultiplies the single-precision floating-point value in the low-order doubleword of first sourceoperand by the single-precision floating-point value in the low-order doubleword of the second sourceoperand and writes the result in the low-order doubleword of the destination (first source).
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