Volume 4 128-Bit Media Instructions (794098), страница 34
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3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePADDD239AMD64 Technology26568—Rev.
3.09—July 2007PADDQPacked Add QuadwordsAdds each packed 64-bit integer value in the first source operand to the corresponding packed 64-bitinteger in the second source operand and writes the integer result of each addition in the correspondingquadword of the destination (first source). The first source/destination operand is an XMM registerand the second source operand is another XMM register or 128-bit memory location.The PADDQ instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePADDQ xmm1, xmm2/mem12866 0F D4 /rDescriptionAdds packed 64-bit integer values in an XMM registerand another XMM register or 128-bit memory locationand writes the result in the destination XMM register.xmm1127xmm2/mem12864 63012764 630addaddpaddq-128.epsThis instruction operates on both signed and unsigned integers. If the result overflows, the carry isignored (neither the overflow nor carry bit in rFLAGS is set), and only the low-order 64 bits of eachresult are written in the destination.Related InstructionsPADDB, PADDD, PADDSB, PADDSW, PADDUSB, PADDUSW, PADDWrFLAGS AffectedNoneMXCSR Flags AffectedNone240PADDQInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePADDQ241AMD64 Technology26568—Rev.
3.09—July 2007PADDSBPacked Add Signed with Saturation BytesAdds each packed 8-bit signed integer value in the first source operand to the corresponding packed 8bit signed integer in the second source operand and writes the signed integer result of each addition inthe corresponding byte of the destination (first source). The first source/destination operand is anXMM register and the second source operand is another XMM register or 128-bit memory location.The PADDSB instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePADDSB xmm1, xmm2/mem128DescriptionAdds packed byte signed integer values in an XMMregister and another XMM register or 128-bit memorylocation and writes the result in the destination XMMregister.66 0F EC /rxmm1127xmm2/mem128............................01270..............addaddsaturatesaturatepaddsb-128.epsFor each packed value in the destination, if the value is larger than the largest representable signed 8bit integer, it is saturated to 7Fh, and if the value is smaller than the smallest signed 8-bit integer, it issaturated to 80h.Related InstructionsPADDB, PADDD, PADDQ, PADDSW, PADDUSB, PADDUSW, PADDWrFLAGS AffectedNoneMXCSR Flags AffectedNone242PADDSBInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePADDSB243AMD64 Technology26568—Rev.
3.09—July 2007PADDSWPacked Add Signed with Saturation WordsAdds each packed 16-bit signed integer value in the first source operand to the corresponding packed16-bit signed integer in the second source operand and writes the signed integer result of each additionin the corresponding word of the destination (first source). The first source/destination operand is anXMM register and the second source operand is another XMM register or 128-bit memory location.The PADDSW instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodePADDSW xmm1, xmm2/mem128DescriptionAdds packed 16-bit signed integer values in an XMMregister and another XMM register or 128-bit memorylocation and writes the result in the destination XMMregister.66 0F ED /rxmm1....xmm2/mem128..127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....0127 112 111 96 95 80 79 64 63 48 47 32 31 16 15......0.addsaturateaddsaturatepaddsw-128.epsFor each packed value in the destination, if the value is larger than the largest representable signed 16bit integer, it is saturated to 7FFFh, and if the value is smaller than the smallest signed 16-bit integer, itis saturated to 8000h.Related InstructionsPADDB, PADDD, PADDQ, PADDSB, PADDUSB, PADDUSW, PADDWrFLAGS AffectedNoneMXCSR Flags AffectedNone244PADDSWInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePADDSW245AMD64 Technology26568—Rev.
3.09—July 2007PADDUSBPacked Add Unsigned with Saturation BytesAdds each packed 8-bit unsigned integer value in the first source operand to the corresponding packed8-bit unsigned integer in the second source operand and writes the unsigned integer result of eachaddition in the corresponding byte of the destination (first source). The first source/destination operandis an XMM register and the second source operand is another XMM register or 128-bit memorylocation.The PADDUSB instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePADDUSB xmm1, xmm2/mem128DescriptionAdds packed byte unsigned integer values in anXMM register and another XMM register or 128-bitmemory location and writes the result in thedestination XMM register.66 0F DC /rxmm1........xmm2/mem128......1270.............127.0..............addaddsaturatesaturatepaddusb-128.epsFor each packed value in the destination, if the value is larger than the largest unsigned 8-bit integer, itis saturated to FFh, and if the value is smaller than the smallest unsigned 8-bit integer, it is saturated to00h.Related InstructionsPADDB, PADDD, PADDQ, PADDSB, PADDSW, PADDUSW, PADDWrFLAGS AffectedNoneMXCSR Flags AffectedNone246PADDUSBInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePADDUSB247AMD64 Technology26568—Rev.
3.09—July 2007PADDUSWPacked Add Unsigned with Saturation WordsAdds each packed 16-bit unsigned integer value in the first source operand to the correspondingpacked 16-bit unsigned integer in the second source operand and writes the unsigned integer result ofeach addition in the corresponding word of the destination (first source).
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