Volume 4 128-Bit Media Instructions (794098), страница 35
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The first source/destinationoperand is an XMM register and the second source operand is another XMM register or 128-bitmemory location.The PADDUSW instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePADDUSW xmm1, xmm2/mem128DescriptionAdds packed 16-bit unsigned integer values in anXMM register and another XMM register or 128-bitmemory location and writes result in the destinationXMM register.66 0F DD /rxmm1....xmm2/mem128..127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....0127 112 111 96 95 80 79 64 63 48 47 32 31 16 15......0.addaddsaturatesaturatepaddusw-128.epsFor each packed value in the destination, if the value is larger than the largest unsigned 16-bit integer,it is saturated to FFFFh, and if the value is smaller than the smallest unsigned 16-bit integer, it issaturated to 0000h.Related InstructionsPADDB, PADDD, PADDQ, PADDSB, PADDSW, PADDUSB, PADDWrFLAGS AffectedNoneMXCSR Flags AffectedNone248PADDUSWInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePADDUSW249AMD64 Technology26568—Rev.
3.09—July 2007PADDWPacked Add WordsAdds each packed 16-bit integer value in the first source operand to the corresponding packed 16-bitinteger in the second source operand and writes the integer result of each addition in the correspondingword of the destination (first source). The first source/destination operand is an XMM register and thesecond source operand is another XMM register or 128-bit memory location.The PADDW instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePADDW xmm1, xmm2/mem128DescriptionAdds packed 16-bit integer values in an XMM registerand another XMM register or 128-bit memory locationand writes the result in the destination XMM register.66 0F FD /rxmm1....xmm2/mem128..127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....0.127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....0.addaddpaddw-128.epsThis instruction operates on both signed and unsigned integers.
If the result overflows, the carry isignored (neither the overflow nor carry bit in rFLAGS is set), and only the low-order 16 bits of theresult are written in the destination.Related InstructionsPADDB, PADDD, PADDQ, PADDSB, PADDSW, PADDUSB, PADDUSWrFLAGS AffectedNoneMXCSR Flags AffectedNone250PADDWInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePADDW251AMD64 Technology26568—Rev.
3.09—July 2007PANDPacked Logical Bitwise ANDPerforms a bitwise logical AND of the values in the first and second source operands and writes theresult in the destination (first source). The first source/destination operand is an XMM register and thesecond source operand is another XMM register or 128-bit memory location.The PAND instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePAND xmm1, xmm2/mem128DescriptionPerforms bitwise logical AND of values in an XMMregister and in another XMM register or 128-bit memorylocation and writes the result in the destination XMMregister.66 0F DB /rxmm1xmm2/mem12812701270ANDpand-128.epsRelated InstructionsPANDN, POR, PXORrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionInvalid opcode, #UD252RealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 is cleared to 0.PANDInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionDevice not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.General protection,#GPXInstruction ReferencePAND253AMD64 Technology26568—Rev.
3.09—July 2007PANDNPacked Logical Bitwise AND NOTPerforms a bitwise logical AND of the value in the second source operand and the one’s complementof the value in the first source operand and writes the result in the destination (first source). The firstsource/destination operand is an XMM register and the second source operand is another XMMregister or 128-bit memory location.The PANDN instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePANDN xmm1, xmm2/mem12866 0F DF /rDescriptionPerforms bitwise logical AND NOT of values in an XMMregister and in another XMM register or 128-bit memorylocation and writes the result in the destination XMMregister.xmm1127xmm2/mem12801270invertANDpandn-128.epsRelated InstructionsPAND, POR, PXORrFLAGS AffectedNoneMXCSR Flags AffectedNone254PANDNInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection,#GPXInstruction ReferencePANDN255AMD64 Technology26568—Rev.
3.09—July 2007PAVGBPacked Average Unsigned BytesComputes the rounded average of each packed unsigned 8-bit integer value in the first source operandand the corresponding packed 8-bit unsigned integer in the second source operand and writes eachaverage in the corresponding byte of the destination (first source). The average is computed by addingeach pair of operands, adding 1 to the 9-bit temporary sum, and then right-shifting the temporary sumby one bit position. The destination and source operands are an XMM register and another XMMregister or 128-bit memory location.The PAVGB instruction is an SSE instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePAVGB xmm1, xmm2/mem128DescriptionAverages packed 8-bit unsigned integer values in anXMM register and another XMM register or 128-bitmemory location and writes the result in thedestination XMM register.66 0F E0 /rxmm1........xmm2/mem128......1270..............1270..............averageaveragepavgb-128.epsRelated InstructionsPAVGWrFLAGS AffectedNoneMXCSR Flags AffectedNone256PAVGBInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePAVGB257AMD64 Technology26568—Rev.
3.09—July 2007PAVGWPacked Average Unsigned WordsComputes the rounded average of each packed unsigned 16-bit integer value in the first source operandand the corresponding packed 16-bit unsigned integer in the second source operand and writes eachaverage in the corresponding word of the destination (first source). The average is computed by addingeach pair of operands, adding 1 to the 17-bit temporary sum, and then right-shifting the temporary sumby one bit position. The first source/destination operand is an XMM register and the second sourceoperand is another XMM register or 128-bit memory location.The PAVGW instruction is an SSE instruction.
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