Volume 4 128-Bit Media Instructions (794098), страница 39
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3.09—July 2007PMOVMSKBPacked Move Mask ByteMoves the most-significant bit of each byte in the source operand to the destination, with zeroextension to 32 bits. The destination and source operands are a 32-bit general-purpose register and anXMM register. The result is written to the low-order word of the general-purpose register.The PMOVMSKB instruction is an SSE2 instruction. The presence of this instruction set is indicatedby a CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePMOVMSKB reg32, xmmDescription66 0F D7 /rMoves most-significant bit of each byte in an XMM registerto low-order word of a 32-bit general-purpose register.reg32xmm........................32150127 119 111 103 95 87 79 71 63 55 47 39 31 23 15 7 00.....copy.... .. ...copypmovmskb-128.epsRelated InstructionsMOVMSKPD, MOVMSKPSrFLAGS AffectedNoneMXCSR Flags AffectedNone286PMOVMSKBInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionInvalid opcode, #UDDevice not available,#NMInstruction ReferenceRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 is cleared to 0.XXXThe task-switch bit (TS) of CR0 was set to 1.PMOVMSKB287AMD64 Technology26568—Rev. 3.09—July 2007PMULHUWPacked Multiply High Unsigned WordMultiplies each packed unsigned 16-bit values in the first source operand by the corresponding packedunsigned word in the second source operand and writes the high-order 16 bits of each intermediate 32bit result in the corresponding word of the destination (first source).
The first source/destinationoperand is an XMM register and the second source operand is another XMM register or 128-bitmemory location.The PMULHUW instruction is an SSE instruction. The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePMULHUW xmm1, xmm2/mem128DescriptionMultiplies packed 16-bit values in an XMM registerby the packed 16-bit values in another XMM registeror 128-bit memory location and writes the high-order16 bits of each result in the destination XMMregister.66 0F E4 /rxmm1....xmm2/mem128..127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....0127 112 111 96 95 80 79 64 63 48 47 32 31 16 15......0.multiplymultiplypmulhuw-128.epsRelated InstructionsPMADDWD, PMULHW, PMULLW, PMULUDQrFLAGS AffectedNoneMXCSR Flags AffectedNone288PMULHUWInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby bit 25 in CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePMULHUW289AMD64 Technology26568—Rev.
3.09—July 2007PMULHWPacked Multiply High Signed WordMultiplies each packed 16-bit signed integer value in the first source operand by the correspondingpacked 16-bit signed integer in the second source operand and writes the high-order 16 bits of theintermediate 32-bit result of each multiplication in the corresponding word of the destination (firstsource). The first source/destination operand is an XMM register and the second source operand isanother XMM register or 128-bit memory location.The PMULHW instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePMULHW xmm1, xmm2/mem128DescriptionMultiplies packed 16-bit signed integer values in anXMM register and another XMM register or 128-bitmemory location and writes the high-order 16 bits ofeach result in the destination XMM register.66 0F E5 /rxmm1....xmm2/mem128..127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....0127 112 111 96 95 80 79 64 63 48 47 32 31 16 15......0.multiplymultiplypmulhw-128.epsRelated InstructionsPMADDWD, PMULHUW, PMULLW, PMULUDQrFLAGS AffectedNoneMXCSR Flags AffectedNone290PMULHWInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePMULHW291AMD64 Technology26568—Rev.
3.09—July 2007PMULLWPacked Multiply Low Signed WordMultiplies each packed 16-bit signed integer value in the first source operand by the correspondingpacked 16-bit signed integer in the second source operand and writes the low-order 16 bits of theintermediate 32-bit result of each multiplication in the corresponding word of the destination (firstsource).
The first source/destination operand is an XMM register and the second source operand isanother XMM register or 128-bit memory location.The PMULLW instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodePMULLW xmm1, xmm2/mem128DescriptionMultiplies packed 16-bit signed integer values in anXMM register and another XMM register or 128-bitmemory location and writes the low-order 16 bits ofeach result in the destination XMM register.66 0F D5 /rxmm1....xmm2/mem128..127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....0127 112 111 96 95 80 79 64 63 48 47 32 31 16 15......0.multiplymultiplypmullw-128.epsRelated InstructionsPMADDWD, PMULHUW, PMULHW, PMULUDQrFLAGS AffectedNoneMXCSR Flags AffectedNone292PMULLWInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePMULLW293AMD64 TechnologyPMULUDQ26568—Rev.
3.09—July 2007Packed Multiply Unsigned Doubleword and StoreQuadwordMultiplies two pairs of 32-bit unsigned integer values in the first and second source operands andwrites the two 64-bit results in the destination (first source). The first source/destination operand is anXMM register and the second source operand is another XMM register or 128-bit memory location.The source operands are in the first (low-order) and third doublewords of the source operands, and theresult of each multiply is stored in the first and second quadwords of the destination XMM register.The PMULUDQ instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePMULUDQ xmm1, xmm2/mem128DescriptionMultiplies two pairs of 32-bit unsigned integer valuesin an XMM register and another XMM register or128-bit memory location and writes the two 64-bitresults in the destination XMM register.66 0F F4 /rxmm112796 9564 63xmm2/mem12832 31012796 9564 6332 310multiplymultiplypmuludq-128.epsRelated InstructionsPMADDWD, PMULHUW, PMULHW, PMULLWrFLAGS AffectedNoneMXCSR Flags AffectedNone294PMULUDQInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPXInstruction ReferencePMULUDQ295AMD64 Technology26568—Rev.
3.09—July 2007PORPacked Logical Bitwise ORPerforms a bitwise logical OR of the values in the first and second source operands and writes theresult in the destination (first source). The first source/destination operand is an XMM register and thesecond source operand is another XMM register or 128-bit memory location.The POR instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePOR xmm1,xmm2/mem128DescriptionPerforms bitwise logical OR of values in an XMM registerand in another XMM register or 128-bit memory location andwrites the result in the destination XMM register.66 0F EB /rxmm1xmm2/mem12812701270ORpor-128.epsRelated InstructionsPAND, PANDN, PXORrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionInvalid opcode, #UD296RealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 is cleared to 0.PORInstruction Reference26568—Rev.
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