Volume 4 128-Bit Media Instructions (794098), страница 41
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3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionDevice not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.General protection, #GPX308PSHUFLWInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyPSLLDPacked Shift Left Logical DoublewordsLeft-shifts each of the packed 32-bit values in the first source operand by the number of bits specifiedin the second source operand and writes each shifted value in the corresponding doubleword of thedestination (first source).
The first source/destination and second source operands are:••an XMM register and another XMM register or 128-bit memory location, oran XMM register and an immediate byte value.The low-order bits that are emptied by the shift operation are cleared to 0. If the shift value is greaterthan 31, the destination is cleared to all 0s.The PSLLD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionPSLLD xmm1,xmm2/mem12866 0F F2 /rLeft-shifts packed doublewords in an XMM registerby the amount specified in the low 64 bits of an XMMregister or 128-bit memory location.PSLLD xmm, imm866 0F 72 /6 ibLeft-shifts packed doublewords in an XMM registerby the amount specified in an immediate byte value.xmm112796 95.64 63.xmm2/mem128.32 31012764 630.shift leftshift leftxmm.12796 95imm8.64 63.32 3107 0.shift leftshift leftpslld-128.epsRelated InstructionsPSLLDQ, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQ, PSRLWInstruction ReferencePSLLD309AMD64 Technology26568—Rev.
3.09—July 2007rFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX310PSLLDInstruction Reference26568—Rev.
3.09—July 2007PSLLDQAMD64 TechnologyPacked Shift Left Logical Double QuadwordLeft-shifts the 128-bit (double quadword) value in an XMM register by the number of bytes specifiedin an immediate byte value. The low-order bytes that are emptied by the shift operation are cleared to0. If the shift value is greater than 15, the destination XMM register is cleared to all 0s.The PSLLDQ instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePSLLDQ xmm, imm866 0F 73 /7 ibDescriptionLeft-shifts double quadword value in an XMM register by theamount specified in an immediate byte value.xmm127imm807 0shift leftpslldq.epsRelated InstructionsPSLLD, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQ, PSRLWrFLAGS AffectedNoneMXCSR Flags AffectedNoneInstruction ReferencePSLLDQ311AMD64 Technology26568—Rev. 3.09—July 2007ExceptionsExceptionInvalid opcode, #UDDevice not available,#NM312RealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.XXXThe task-switch bit (TS) of CR0 was set to 1.PSLLDQInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyPSLLQPacked Shift Left Logical QuadwordsLeft-shifts each 64-bit value in the first source operand by the number of bits specified in the secondsource operand and writes each shifted value in the corresponding quadword of the destination (firstsource). The first source/destination and second source operands are:••an XMM register and another XMM register or 128-bit memory location, oran XMM register and an immediate byte value.The low-order bits that are emptied by the shift operation are cleared to 0.
If the shift value is greaterthan 63, the destination is cleared to all 0s.The PSLLQ instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionPSLLQ xmm1, xmm2/mem12866 0F F3 /rLeft-shifts packed quadwords in XMM register by theamount specified in the low 64 bits of an XMMregister or 128-bit memory location.PSLLQ xmm, imm866 0F 73 /6 ibLeft-shifts packed quadwords in an XMM register bythe amount specified in an immediate byte value.xmm1127xmm2/mem12864 63012764 630shift leftshift leftxmm127imm864 6307 0shift leftshift leftpsllq-128.epsRelated InstructionsPSLLD, PSLLDQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQ, PSRLWInstruction ReferencePSLLQ313AMD64 Technology26568—Rev.
3.09—July 2007rFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX314PSLLQInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyPSLLWPacked Shift Left Logical WordsLeft-shifts each of the packed 16-bit values in the first source operand by the number of bits specifiedin the second source operand and writes each shifted value in the corresponding word of thedestination (first source). The first source/destination and second source operands are:••an XMM register and another XMM register or 128-bit memory location, oran XMM register and an immediate byte valueThe low-order bits that are emptied by the shift operation are cleared to 0. If the shift value is greaterthan 15, the destination is cleared to all 0s.The PSLLW instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionPSLLW xmm1,xmm2/mem12866 0F F1 /rLeft-shifts packed words in an XMM register by theamount specified in the low 64 bits of an XMMregister or 128-bit memory location.PSLLW xmm, imm866 0F 71 /6 ibLeft-shifts packed words in an XMM register by theamount specified in an immediate byte value.xmm1...xmm2/mem128...127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....012764 630.shift leftshift leftxmm...imm8...127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....07 0.shift leftshift leftpsllw-128.epsInstruction ReferencePSLLW315AMD64 Technology26568—Rev.
3.09—July 2007Related InstructionsPSLLD, PSLLDQ, PSLLQ, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQ, PSRLWrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX316PSLLWInstruction Reference26568—Rev.
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