Volume 4 128-Bit Media Instructions (794098), страница 30
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3.09—July 2007AMD64 Technologyxmm1127xmm264 63012764 630copyxmm1127mem6464 6363000copymem64xmm263012764 630copymovsd.epsRelated InstructionsMOVAPD, MOVHPD, MOVLPD, MOVMSKPD, MOVUPDrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionInvalid opcode, #UDDevice not available,#NMInstruction ReferenceRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.XXXThe task-switch bit (TS) of CR0 was set to 1.MOVSD201AMD64 TechnologyExceptionStack, #SS26568—Rev.
3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.202MOVSDInstruction Reference26568—Rev.
3.09—July 2007MOVSHDUPAMD64 TechnologyMove Single-Precision High and DuplicateMoves two copies of the second doubleword of data in the source XMM register or 128-bit memoryoperand to bits 31–0 and bits 63–32 of the destination XMM register; moves two copies of the fourthdoubleword of data in the source operand to bits 95–64 and bits 127–96 of the destination XMMregister.The MOVSHDUP instruction is an SSE3 instruction. The presence of this instruction set is indicatedby a CPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeMOVSHDUP xmm1,xmm2/mem128F3 0F 16 /rDescriptionCopies the second 32-bits from the source operand tothe first and second 32-bit segments of the destinationXMM register; copies the fourth 32-bits from the sourceoperand to the third and fourth 32-bit segments of thedestination XMM register.xmm112796 9564 63xmm2/mem12832 31012796 9564 6332 310Related InstructionsMOVDDUP, MOVSLDUPrFLAGS AffectedNoneMXCSR Flags AffectedNoneInstruction ReferenceMOVSHDUP203AMD64 Technology26568—Rev. 3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE3 instructions are not supported, asindicated by ECX bit 0 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.Invalid opcode, #UDGeneral protection, #GPX204MOVSHDUPInstruction Reference26568—Rev.
3.09—July 2007MOVSLDUPAMD64 TechnologyMove Single-Precision Low and DuplicateMoves two copies of the first doubleword of data in the source XMM register or 128-bit memoryoperand to bits 31–0 and bits 32–63 of the destination XMM register and moves two copies of the thirddoubleword of data in the source operand to bits 95–64 and bits 127–96 of the destination XMMregister.The MOVSLDUP instruction is an SSE3 instruction. The presence of this instruction set is indicatedby a CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeMOVSLDUP xmm1,xmm2/mem128F3 0F 12 /rDescriptionCopies the first 32-bits from the source operand to thefirst and second 32-bit segments of the destinationXMM register; copies the third 32-bits from the sourceoperand to the third and fourth 32-bit segments of thedestination XMM register.xmm112796 9564 63xmm2/mem12832 31012796 9564 6332 310Related InstructionsMOVDDUP, MOVSHDUPrFLAGS AffectedNoneMXCSR Flags AffectedNoneInstruction ReferenceMOVSLDUP205AMD64 Technology26568—Rev.
3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE3 instructions are not supported, asindicated by ECX bit 0 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.Invalid opcode, #UDGeneral protection, #GPX206MOVSLDUPInstruction Reference26568—Rev.
3.09—July 2007MOVSSAMD64 TechnologyMove Scalar Single-Precision Floating-PointMoves a scalar single-precision floating-point value:••from the low-order 32 bits of an XMM register or a 32-bit memory location to the low-order 32 bitsof another XMM register, orfrom a 32-bit memory location to the low-order 32 bits of an XMM register, with zero-extension to128 bits.If the source operand is an XMM register, the high-order 96 bits of the destination XMM register arenot modified. If the source operand is a memory location, the high-order 96 bits of the destinationXMM register are cleared to all 0s.The MOVSS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionMOVSS xmm1, xmm2/mem32F3 0F 10 /rMoves single-precision floating-point value from an XMMregister or 32-bit memory location to an XMM register.MOVSS xmm1/mem32, xmm2F3 0F 11 /rMoves single-precision floating-point value from an XMMregister to an XMM register or 32-bit memory location.xmm1127xmm232 31012732 310copyxmm1127mem3232 3103100copymem3231xmm2012732 310copymovss.epsInstruction ReferenceMOVSS207AMD64 Technology26568—Rev.
3.09—July 2007Related InstructionsMOVAPS, MOVHLPS, MOVHPS, MOVLHPS, MOVLPS, MOVMSKPS, MOVUPSrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.Invalid opcode, #UDGeneral protection,#GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.208MOVSSInstruction Reference26568—Rev.
3.09—July 2007MOVUPDAMD64 TechnologyMove Unaligned Packed Double-PrecisionFloating-PointMoves two packed double-precision floating-point values:••from an XMM register or 128-bit memory location to another XMM register, orfrom an XMM register to another XMM register or 128-bit memory location.Memory operands that are not aligned on a 16-byte boundary do not cause a general-protectionexception.The MOVUPD instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionMOVUPD xmm1, xmm2/mem12866 0F 10 /rMoves two packed double-precision floating-pointvalues from an XMM register or unaligned 128-bitmemory location to an XMM register.MOVUPD xmm1/mem128, xmm266 0F 11 /rMoves two packed double-precision floating-pointvalues from an XMM register to an XMM register orunaligned 128-bit memory location.xmm112764 63xmm2/mem28012764 63copyxmm1/mem2812764 630copyxmm2012764 63copycopymovupd.epsInstruction ReferenceMOVUPD209AMD64 Technology26568—Rev. 3.09—July 2007Related InstructionsMOVAPD, MOVHPD, MOVLPD, MOVMSKPD, MOVSDrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.Invalid opcode, #UDGeneral protection,#GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.210MOVUPDInstruction Reference26568—Rev.
3.09—July 2007MOVUPSAMD64 TechnologyMove Unaligned Packed Single-PrecisionFloating-PointMoves four packed single-precision floating-point values:••from an XMM register or 128-bit memory location to another XMM register, orfrom an XMM register to another XMM register or 128-bit memory location.Memory operands that are not aligned on a 16-byte boundary do not cause a general-protectionexception.The MOVUPS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionMOVUPS xmm1, xmm2/mem1280F 10 /rMoves four packed single-precision floating-point valuesfrom an XMM register or unaligned 128-bit memorylocation to an XMM register.MOVUPS xmm1/mem128, xmm20F 11 /rMoves four packed single-precision floating-point valuesfrom an XMM register to an XMM register or unaligned128-bit memory location.Instruction ReferenceMOVUPS211AMD64 Technology26568—Rev.
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