Volume 4 128-Bit Media Instructions (794098), страница 24
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If eitheroperand is a NaN (SNaN or QNaN), and invalid-operation exceptions are masked, the second sourceoperand is written to the destination.The MAXSD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeMAXSD xmm1, xmm2/mem64F2 0F 5F /rDescriptionCompares scalar double-precision values in an XMMregister and another XMM register or 64-bit memorylocation and writes the greater of the two values in thedestination XMM register.xmm1127xmm2/mem6464 63012764 630maximummaxsd.epsRelated InstructionsMAXPD, MAXPS, MAXSS, MINPD, MINPS, MINSD, MINSSrFLAGS AffectedNone142MAXSDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZPE65UE4OEZE32DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions for details.SIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN or QNaN value.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Instruction ReferenceMAXSD143AMD64 TechnologyMAXSS26568—Rev.
3.09—July 2007Maximum Scalar Single-Precision Floating-PointCompares the single-precision floating-point value in the low-order 32 bits of the first source operandwith the single-precision floating-point value in the low-order 32 bits of the second source operand andwrites the numerically greater of the two values in the low-order 32 bits of the destination (firstsource). The first source/destination operand is an XMM register. The second source operand isanother XMM register or a 32-bit memory location. The three high-order doublewords of thedestination XMM register are not modified.If both source operands are equal to zero, the value in the second source operand is returned.
If eitheroperand is a NaN (SNaN or QNaN), and invalid-operation exceptions are masked, the second sourceoperand is written to the destination.The MAXSS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeMAXSS xmm1, xmm2/mem32DescriptionF3 0F 5F /rCompares scalar single-precision floating-point values inan XMM register and another XMM register or 32-bitmemory location and writes the greater of the two valuesin the destination XMM register.xmm1127xmm2/mem3232 31012732 310maximummaxss.epsRelated InstructionsMAXPD, MAXPS, MAXSD, MINPD, MINPS, MINSD, MINSS, PFMAXrFLAGS AffectedNone144MAXSSInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZPE65UE4OEZE32DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions for details.SIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN or QNaN value.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Instruction ReferenceMAXSS145AMD64 TechnologyMINPD26568—Rev.
3.09—July 2007Minimum Packed Double-Precision Floating-PointCompares each of the two packed double-precision floating-point values in the first source operandwith the corresponding packed double-precision floating-point value in the second source operand andwrites the numerically lesser of the two values for each comparison in the corresponding quadword ofthe destination (first source).
The first source/destination operand is an XMM register. The secondsource operand is another XMM register or a 128-bit memory location.If both source operands are equal to zero, the value in the second source operand is returned. If eitheroperand is a NaN (SNaN or QNaN), and invalid-operation exceptions are masked, the second sourceoperand is written to the destination.The MINPD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeMINPD xmm1, xmm2/mem12866 0F 5D /rDescriptionCompares two pairs of packed double-precision floatingpoint values in an XMM register and another XMMregister or 128-bit memory location and writes thelesser value of each comparison in the destination XMMregister.xmm1127xmm2/mem12864 63012764 630minimumminimumminpd.epsRelated InstructionsMAXPD, MAXPS, MAXSD, MAXSS, MINPS, MINSD, MINSSrFLAGS AffectedNone146MINPDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZPE65UE4OEZE32DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled and MXCSR.MMwas set to 1.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN or QNaN value.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Instruction ReferenceMINPD147AMD64 TechnologyMINPS26568—Rev.
3.09—July 2007Minimum Packed Single-Precision Floating-PointThe MINPS instruction compares each of the four packed single-precision floating-point values in thefirst source operand with the corresponding packed single-precision floating-point value in the secondsource operand and writes the numerically lesser of the two values for each comparison in thecorresponding doubleword of the destination (first source). The first source/destination operand is anXMM register. The second source operand is another XMM register or a 128-bit memory location.If both source operands are equal to zero, the value in the second source operand is returned.
If eitheroperand is a NaN (SNaN or QNaN), and invalid-operation exceptions are masked, the second sourceoperand is written to the destination.The MINPS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeMINPS xmm1,xmm2/mem1280F 5D /rDescriptionCompares four pairs of packed single-precision values in anXMM register and another XMM register or 128-bit memorylocation and writes the numerically lesser value of eachcomparison in the destination XMM register.xmm112796 9564 63xmm2/mem12832 31012796 9564 6332 310minimumminimumminimumminimumminps.epsRelated InstructionsMAXPD, MAXPS, MAXSD, MAXSS, MINPD, MINSD, MINSS, PFMINrFLAGS AffectedNone148MINPSInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZPE65UE4OEZE32DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified).
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