Volume 4 128-Bit Media Instructions (794098), страница 46
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3.09—July 2007AMD64 TechnologyPUNPCKLBWUnpack and Interleave Low BytesUnpacks the low-order bytes from the first and second source operands and packs them intointerleaved bytes in the destination (first source). The high-order bytes of the source operands areignored. The first source/destination operand is an XMM register and the second source operand isanother XMM register or 128-bit memory location.If the second source operand is all 0s, the destination contains the bytes from the first source operandzero-extended to 16 bits. This operation is useful for expanding unsigned 8-bit values to unsigned 16bit operands for subsequent processing that requires higher precision.The PUNPCKLBW instruction is an SSE2 instruction.
The presence of this instruction set is indicatedby a CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePUNPCKLBW xmm1,xmm2/mem128DescriptionUnpacks the eight low-order bytes in an XMMregister and another XMM register or 128-bitmemory location and packs them into interleavedbytes in the destination XMM register.66 0F 60 /rxmm1127xmm2/mem12864 630.
....64 63.copy....0. .copy127127.. .copy..64 63......copy.0punpcklbw-128.epsRelated InstructionsP U N P C K H B W, P U N P C K H D Q , P U N P C K H Q D Q , P U N P C K H W D , P U N P C K L D Q ,PUNPCKLQDQ, PUNPCKLWDrFLAGS AffectedNoneInstruction ReferencePUNPCKLBW353AMD64 Technology26568—Rev. 3.09—July 2007MXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX354PUNPCKLBWInstruction Reference26568—Rev.
3.09—July 2007PUNPCKLDQAMD64 TechnologyUnpack and Interleave Low DoublewordsUnpacks the low-order doublewords from the first and second source operands and packs them intointerleaved doublewords in the destination (first source). The high-order doublewords of the sourceoperands are ignored. The first source/destination operand is an XMM register and the second sourceoperand is another XMM register or 128-bit memory location.If the second source operand is all 0s, the destination contains the doubleword(s) from the first sourceoperand zero-extended to 64 bits. This operation is useful for expanding unsigned 32-bit values tounsigned 64-bit operands for subsequent processing that requires higher precision.The PUNPCKLDQ instruction is an SSE2 instruction. The presence of this instruction set is indicatedby a CPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodePUNPCKLDQ xmm1,xmm2/mem128DescriptionUnpacks two low-order doublewords in an XMMregister and another XMM register or 128-bit memorylocation and packs them into interleaved doublewordsin the destination XMM register.66 0F 62 /rxmm1127xmm2/mem12864 6332 31copy1270127copy96 9564 6332 31064 6332 31copycopy0punpckldq-128.epsRelated InstructionsP U N P C K H B W, P U N P C K H D Q , P U N P C K H Q D Q , P U N P C K H W D , P U N P C K L B W,PUNPCKLQDQ, PUNPCKLWDrFLAGS AffectedNoneInstruction ReferencePUNPCKLDQ355AMD64 Technology26568—Rev. 3.09—July 2007MXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX356PUNPCKLDQInstruction Reference26568—Rev.
3.09—July 2007PUNPCKLQDQAMD64 TechnologyUnpack and Interleave Low QuadwordsUnpacks the low-order quadwords from the first and second source operands and packs them intointerleaved quadwords in the destination (first source). The first source/destination is an XMMregister, and the second source operand is another XMM register or 128-bit memory location. Thehigh-order quadwords of the source operands are ignored.If the second source operand is all 0s, the destination contains the quadword from the first sourceoperand zero-extended to 128 bits.
This operation is useful for expanding unsigned 64-bit values tounsigned 128-bit operands for subsequent processing that requires higher precision.The PUNPCKLQDQ instruction is an SSE2 instruction. The presence of this instruction set isindicated by a CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePUNPCKLQDQ xmm1, xmm2/mem128DescriptionUnpacks low-order quadwords in an XMMregister and another XMM register or 128-bitmemory location and packs them intointerleaved quadwords in the destination XMMregister.66 0F 6C /rxmm1127xmm2/mem12864 63012764 63copy1270copy64 630punpcklqdq.epsRelated InstructionsPUNPCKHBW, PUNPCKHDQ, PUNPCKHQDQ, PUNPCKHWD, PUNPCKLBW, PUNPCKLDQ,PUNPCKLWDrFLAGS AffectedNoneInstruction ReferencePUNPCKLQDQ357AMD64 Technology26568—Rev.
3.09—July 2007MXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX358PUNPCKLQDQInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyPUNPCKLWDUnpack and Interleave Low WordsUnpacks the low-order words from the first and second source operands and packs them intointerleaved words in the destination (first source). The high-order words of the source operands areignored. The first source/destination operand is an XMM register and the second source operand isanother XMM register or 128-bit memory location.If the second source operand is all 0s, the destination contains the words from the first source operandzero-extended to 32 bits.
This operation is useful for expanding unsigned 16-bit values to unsigned 32bit operands for subsequent processing that requires higher precision.The PUNPCKLWD instruction is an SSE2 instruction. The presence of this instruction set is indicatedby a CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePUNPCKLWD xmm1,xmm2/mem128DescriptionUnpacks the four low-order words in an XMMregister and another XMM register or 128-bitmemory location and packs them into interleavedwords in the destination XMM register.66 0F 61 /rxmm1127xmm2/mem12864 63 48 47 32 31 16 15.012764 63 48 47 32 31 16 15..copycopy..copy.0.copy.. 111.
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