Volume 4 128-Bit Media Instructions (794098), страница 50
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3.09—July 2007AMD64 TechnologyVirtual8086 ProtectedExceptionRealOverflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Underflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.Instruction ReferenceCause of ExceptionSUBPD387AMD64 Technology26568—Rev. 3.09—July 2007SUBPSSubtract Packed Single-Precision Floating-PointSubtracts each packed single-precision floating-point value in the second source operand from thecorresponding packed single-precision floating-point value in the first source operand and writes theresult of each subtraction in the corresponding doubleword of the destination (first source).
The firstsource/destination operand is an XMM register. The second source operand is another XMM registeror 128-bit memory location.The SUBPS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeSUBPS xmm1,xmm2/mem1280F 5C /rDescriptionSubtracts packed single-precision floating-point values in anXMM register or 128-bit memory location from packedsingle-precision floating-point values in another XMMregister and writes the result in the destination XMMregister.xmm112796 95xmm2/mem12864 6332 31012796 9564 6332 310subtractsubtractsubtractsubtractsubps.epsRelated InstructionsSUBPD, SUBSD, SUBSSrFLAGS AffectedNone388SUBPSInstruction Reference26568—Rev. 3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEMMM543ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Denormalized-operandexception (DE)Instruction ReferenceXXXA source operand was an SNaN value.XXX+infinity was subtracted from +infinity.XXX–infinity was subtracted from –infinity.XXXA source operand was a denormal value.SUBPS389AMD64 Technology26568—Rev.
3.09—July 2007Virtual8086 ProtectedExceptionRealOverflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Underflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.390Cause of ExceptionSUBPSInstruction Reference26568—Rev. 3.09—July 2007SUBSDAMD64 TechnologySubtract Scalar Double-Precision Floating-PointSubtracts the double-precision floating-point value in the low-order quadword of the second sourceoperand from the double-precision floating-point value in the low-order quadword of the first sourceoperand and writes the result in the low-order quadword of the destination (first source).
The highorder quadword of the destination is not modified. The first source/destination operand is an XMMregister. The second source operand is another XMM register or 64-bit memory location.The SUBSD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeSUBSD xmm1,xmm2/mem64F2 0F 5C /rDescriptionSubtracts low-order double-precision floating-point valuein an XMM register or in a 64-bit memory location fromlow-order double-precision floating-point value in anotherXMM register and writes the result in the destinationXMM register.xmm1127xmm2/mem6464 63012764 630subtractsubsd.epsRelated InstructionsSUBPD, SUBPS, SUBSSrFLAGS AffectedNoneInstruction ReferenceSUBSD391AMD64 Technology26568—Rev. 3.09—July 2007MXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEMMM543ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified).
Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsXXXA source operand was an SNaN value.XXX+infinity was subtracted from +infinity.XXX–infinity was subtracted from –infinity.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Invalid-operationexception (IE)392SUBSDInstruction Reference26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionUnderflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.Instruction ReferenceSUBSD393AMD64 Technology26568—Rev. 3.09—July 2007SUBSSSubtract Scalar Single-Precision Floating-PointSubtracts the single-precision floating-point value in the low-order doubleword of the second sourceoperand from the single-precision floating-point value in the low-order doubleword of the first sourceoperand and writes the result in the low-order doubleword of the destination (first source).
The threehigh-order doublewords of the destination are not modified. The first source/destination operand is anXMM register. The second source operand is another XMM register or 32-bit memory location.The SUBSS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeSUBSS xmm1,xmm2/mem32DescriptionF3 0F 5C /rSubtracts low-order single-precision floating-point valuein an XMM register or in a 32-bit memory location fromlow-order single-precision floating-point value in anotherXMM register and writes the result in the destinationXMM register.xmm1127xmm2/mem3232 31012732 310subtractsubss.epsRelated InstructionsSUBPD, SUBPS, SUBSDrFLAGS AffectedNone394SUBSSInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEMMM543ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsXXXA source operand was an SNaN value.XXX+infinity was subtracted from +infinity.XXX–infinity was subtracted from –infinity.Denormalized-operandexception (DE)XXXA source operand was a denormal value.Overflow exception (OE)XXXA rounded result was too large to fit into the format ofthe destination operand.Invalid-operationexception (IE)395AMD64 TechnologyException26568—Rev.
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