Volume 4 128-Bit Media Instructions (794098), страница 49
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3.09—July 2007SQRTSDSquare Root Scalar Double-PrecisionFloating-PointComputes the square root of the low-order double-precision floating-point value in an XMM registeror in a 64-bit memory location and writes the result in the low-order quadword of another XMMregister. The high-order quadword of the destination XMM register is not modified. Taking the squareroot of +infinity returns +infinity.The SQRTSD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeSQRTSD xmm1, xmm2/mem64F2 0F 51 /rDescriptionComputes square root of double-precision floating-pointvalue in an XMM register or 64-bit memory location andwrites the result in the destination XMM register.xmm112764 63xmm2/mem64012764 630square rootsqrtsd.epsRelated InstructionsRSQRTPS, RSQRTSS, SQRTPD, SQRTPS, SQRTSSrFLAGS AffectedNone380SQRTSDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEM1715141312111098765432DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.Exceptions.ExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsXXXA source operand was an SNaN value.XXXA source operand was negative (not including –0).Denormalized-operandexception (DE)XXXA source operand was a denormal value.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.Invalid-operationexception (IE)Instruction ReferenceSQRTSD381AMD64 Technology26568—Rev.
3.09—July 2007SQRTSSSquare Root Scalar Single-PrecisionFloating-PointComputes the square root of the low-order single-precision floating-point value in an XMM register or32-bit memory location and writes the result in the low-order doubleword of another XMM register.The three high-order doublewords of the destination XMM register are not modified. Taking thesquare root of +infinity returns +infinity.The SQRTSS instruction is an SSE instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeSQRTSS xmm1, xmm2/mem32F3 0F 51 /rDescriptionComputes square root of single-precision floating-pointvalue in an XMM register or 32-bit memory location andwrites the result in the destination XMM register.xmm1127xmm2/mem3232 31012732 310square rootsqrtss.epsRelated InstructionsRSQRTPS, RSQRTSS, SQRTPD, SQRTPS, SQRTSDrFLAGS AffectedNone382SQRTSSInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEM1715141312111098765432DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXSIMD Floating-Point ExceptionsXXXA source operand was an SNaN value.XXXA source operand was negative (not including –0).Denormalized-operandexception (DE)XXXA source operand was a denormal value.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.Invalid-operationexception (IE)Instruction ReferenceSQRTSS383AMD64 Technology26568—Rev.
3.09—July 2007STMXCSRStore MXCSR Control/Status RegisterSaves the contents of the MXCSR register in a 32-bit location in memory. The MXCSR register isdescribed in “Registers” in Volume 1.The STMXCSR instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeSTMXCSR mem32Description0F AE /3Stores contents of MXCSR in 32-bit memory location.Related InstructionsLDMXCSRrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.384STMXCSRInstruction Reference26568—Rev.
3.09—July 2007SUBPDAMD64 TechnologySubtract Packed Double-Precision Floating-PointSubtracts each packed double-precision floating-point value in the second source operand from thecorresponding packed double-precision floating-point value in the first source operand and writes theresult of each subtraction in the corresponding quadword of the destination (first source). The firstsource/destination operand is an XMM register.
The second source operand is another XMM registeror 128-bit memory location.The SUBPD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeSUBPD xmm1,xmm2/mem12866 0F 5C /rDescriptionSubtracts packed double-precision floating-point valuesin an XMM register or 128-bit memory location frompacked double-precision floating-point values in anotherXMM register and writes the result in the destinationXMM register.xmm1127xmm2/mem12864 63012764 630subtractsubtractsubpd.epsRelated InstructionsSUBPS, SUBSD, SUBSSrFLAGS AffectedNoneInstruction ReferenceSUBPD385AMD64 Technology26568—Rev.
3.09—July 2007MXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PEUEOEMMM543ZE2DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXSIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Denormalized-operandexception (DE)386XXXA source operand was an SNaN value.XXX+infinity was subtracted from +infinity.XXX–infinity was subtracted from –infinity.XXXA source operand was a denormal value.SUBPDInstruction Reference26568—Rev.
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