Volume 4 128-Bit Media Instructions (794098), страница 47
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96. 95. 80. 79. 64 63 48. 47. 32. 31. 16. 15.127 1120punpcklwd-128.epsRelated InstructionsPUNPCKHBW, PUNPCKHDQ, PUNPCKHQDQ, PUNPCKHWD, PUNPCKLBW, PUNPCKLDQ,PUNPCKLQDQrFLAGS AffectedNoneInstruction ReferencePUNPCKLWD359AMD64 Technology26568—Rev. 3.09—July 2007MXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX360PUNPCKLWDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyPXORPacked Logical Bitwise Exclusive ORPerforms a bitwise exclusive OR of the values in the first and second source operands and writes theresult in the destination (first source). The first source/destination operand is an XMM register and thesecond source operand is another XMM register or 128-bit memory location.The PXOR instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePXOR xmm1,xmm2/mem128DescriptionPerforms bitwise logical XOR of values in an XMM registerand in another XMM register or 128-bit memory locationand writes the result in the destination XMM register.66 0F EF /rxmm1xmm2/mem12812701270XORpxor-128.epsRelated InstructionsPAND, PANDN, PORrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionInvalid opcode, #UDInstruction ReferenceRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 is cleared to 0.PXOR361AMD64 TechnologyException26568—Rev.
3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionDevice not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.General protection,#GPX362PXORInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyRCPPSReciprocal Packed Single-PrecisionFloating-PointComputes the approximate reciprocal of each of the four packed single-precision floating-point valuesin an XMM register or 128-bit memory location and writes the result in the corresponding doublewordof another XMM register. The rounding control bits (RC) in the MXCSR register have no effect on theresult.The maximum error is less than or equal to 1.5 * 2–12 times the true reciprocal. A source value that is±zero or denormal returns an infinity of the source value’s sign.
Results that underflow are changed tosigned zero. For both SNaN and QNaN source operands, a QNaN is returned.The RCPPS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeRCPPS xmm1,xmm2/mem1280F 53 /rDescriptionComputes reciprocals of packed single-precision floatingpoint values in an XMM register or 128-bit memory locationand writes result in the destination XMM register.xmm112796 9564 63xmm2/mem12832 31012796 9564 6332 310reciprocalreciprocalreciprocalreciprocalrcpps.epsRelated InstructionsRCPSS, RSQRTPS, RSQRTSSrFLAGS AffectedNoneMXCSR Flags AffectedNoneInstruction ReferenceRCPPS363AMD64 Technology26568—Rev. 3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX364RCPPSInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyRCPSSReciprocal Scalar Single-PrecisionFloating-PointComputes the approximate reciprocal of the low-order single-precision floating-point value in anXMM register or in a 32-bit memory location and writes the result in the low-order doubleword ofanother XMM register. The three high-order doublewords in the destination XMM register are notmodified.
The rounding control bits (RC) in the MXCSR register have no effect on the result.The maximum error is less than or equal to 1.5 * 2–12 times the true reciprocal. A source value that is±zero or denormal returns an infinity of the source value’s sign.
Results that underflow are changed tosigned zero. For both SNaN and QNaN source operands, a QNaN is returned.The RCPSS instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeRCPSS xmm1,xmm2/mem32F3 0F 53 /rDescriptionComputes reciprocal of scalar single-precision floatingpoint value in an XMM register or 32-bit memory locationand writes the result in the destination XMM register.xmm1127xmm2/mem3232 31012732 310reciprocalrcpss.epsRelated InstructionsRCPPS, RSQRTPS, RSQRTSSrFLAGS AffectedNoneMXCSR Flags AffectedNoneInstruction ReferenceRCPSS365AMD64 Technology26568—Rev.
3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.366RCPSSInstruction Reference26568—Rev.
3.09—July 2007RSQRTPSAMD64 TechnologyReciprocal Square Root Packed Single-PrecisionFloating-PointComputes the approximate reciprocal of the square root of each of the four packed single-precisionfloating-point values in an XMM register or 128-bit memory location and writes the result in thecorresponding doubleword of another XMM register. The rounding control bits (RC) in the MXCSRregister have no effect on the result.The maximum error is less than or equal to 1.5 * 2–12 times the true reciprocal square root. A sourcevalue that is ±zero or denormal returns an infinity of the source value’s sign.
Negative source valuesother than –zero and –denormal return a QNaN floating-point indefinite value (“Indefinite Values” inVolume 1). For both SNaN and QNaN source operands, a QNaN is returned.The RSQRTPS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeRSQRTPS xmm1, xmm2/mem1280F 52 /rDescriptionComputes reciprocals of square roots of packedsingle-precision floating-point values in an XMMregister or 128-bit memory location and writes theresult in the destination XMM register.xmm112796 9564 63xmm2/mem12832 31012796 95reciprocalsquare root64 63reciprocalsquare root32 31reciprocalsquare root0reciprocalsquare rootrsqrtps.epsRelated InstructionsRSQRTSS, SQRTPD, SQRTPS, SQRTSD, SQRTSSrFLAGS AffectedNoneInstruction ReferenceRSQRTPS367AMD64 Technology26568—Rev.
3.09—July 2007MXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX368RSQRTPSInstruction Reference26568—Rev.
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