Volume 4 128-Bit Media Instructions (794098), страница 51
Текст из файла (страница 51)
3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionUnderflow exception(UE)XXXA rounded result was too small to fit into the format ofthe destination operand.Precision exception(PE)XXXA result could not be represented exactly in thedestination format.39626568—Rev. 3.09—July 2007AMD64 TechnologyUCOMISDUnordered Compare ScalarDouble-Precision Floating-PointPerforms an unordered compare of the double-precision floating-point value in the low-order 64 bits ofan XMM register with the double-precision floating-point value in the low-order 64 bits of anotherXMM register or a 64-bit memory location and sets the ZF, PF, and CF bits in the rFLAGS register toreflect the result of the compare. The OF, AF, and SF bits in rFLAGS are set to zero.
The result isunordered if one or both of the operand values is a NaN.If the instruction causes an unmasked SIMD floating-point exception (#XF), the rFLAGS bits are notupdated.The UCOMISD instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeUCOMISD xmm1, xmm2/mem64DescriptionCompares scalar double-precision floating-pointvalues in an XMM register and an XMM register or 64bit memory location. Sets rFLAGS.66 0F 2E /rxmm1127xmm2/mem6464 63012764 630compare63310Result of Compare0rFLAGSucomisd.epsZFPFCFUnordered111Greater Than000Less Than001Equal100Related InstructionsCMPPD, CMPPS, CMPSD, CMPSS, COMISD, COMISS, UCOMISS397AMD64 Technology26568—Rev.
3.09—July 2007rFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCF0M0MM7642002120191817161413–12111098Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Note: If the instruction causes an unmasked SIMD floating-point exception (#XF), the rFLAGS bits are not updated.MXCSR Flags AffectedMM17FZ15RC14PM1312UMOM1110ZMDM98IM7DAZ6PE5UE4OEZE32DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.General protection, #GPPage fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XF398X26568—Rev.
3.09—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN value.Denormalized-operandexception (DE)XXXA source operand was a denormal value.399AMD64 Technology26568—Rev. 3.09—July 2007UCOMISSUnordered Compare ScalarSingle-Precision Floating-PointPerforms an unordered compare of the single-precision floating-point value in the low-order 32 bits ofan XMM register with the single-precision floating-point value in the low-order 32 bits of anotherXMM register or a 32-bit memory location and sets the ZF, PF, and CF bits in the rFLAGS register toreflect the result.
The OF, AF, and SF bits in rFLAGS are set to zero. The result is unordered if one orboth of the operand values is a NaN.If the instruction causes an unmasked SIMD floating-point exception (#XF), the rFLAGS bits are notupdated.The UCOMISS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeUCOMISS xmm1, xmm2/mem320F 2E /rDescriptionCompares scalar single-precision floating-point values inan XMM register and an XMM register or 32-bit memorylocation. Sets rFLAGS.xmm1xmm2/mem32127310127310compare63310Result of Compare0rFLAGSucomiss.epsZFPFCFUnordered111Greater Than000Less Than001Equal100Related InstructionsCMPPD, CMPPS, CMPSD, CMPSS, COMISD, COMISS, UCOMISD40026568—Rev.
3.09—July 2007AMD64 TechnologyrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCF0M0MM7642002120191817161413–12111098Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank.Note: If the instruction causes an unmasked SIMD floating-point exception (#XF), the rFLAGS bits are not updated.MXCSR Flags AffectedMM17FZ15RC14PM1312UM11OM10ZMDM98IM7DAZ6PE5UE4OEZE32DEIEMM10Note: A flag that may be set to one or cleared to zero is M (modified).
Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.General protection,#GPXXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.SIMD Floating-PointException, #XFXX401AMD64 TechnologyException26568—Rev.
3.09—July 2007RealVirtual8086 ProtectedCause of ExceptionSIMD Floating-Point ExceptionsInvalid-operationexception (IE)XXXA source operand was an SNaN value.Denormalized-operandexception (DE)XXXA source operand was a denormal value.40226568—Rev. 3.09—July 2007UNPCKHPDAMD64 TechnologyUnpack High Double-Precision Floating-PointUnpacks the high-order double-precision floating-point values in the first and second source operandsand packs them into quadwords in the destination (first source). The value from the first sourceoperand is packed into the low-order quadword of the destination, and the value from the secondsource operand is packed into the high-order quadword of the destination.
The low-order quadwords ofthe source operands are ignored. The first source/destination operand is an XMM register. The secondsource operand is another XMM register or 128-bit memory location.The UNPCKHPD instruction is an SSE2 instruction. The presence of this instruction set is indicatedby a CPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeUNPCKHPD xmm1, xmm2/mem128DescriptionUnpacks high-order double-precision floating-pointvalues in an XMM register and another XMMregister or 128-bit memory location and packs theminto the destination XMM register.66 0F 15 /rxmm1127xmm2/mem12864 630127copy64 630copy12764 630unpckhpd.epsRelated InstructionsUNPCKHPS, UNPCKLPD, UNPCKLPSrFLAGS AffectedNoneMXCSR Flags AffectedNone403AMD64 Technology26568—Rev. 3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDXX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX40426568—Rev.
3.09—July 2007UNPCKHPSAMD64 TechnologyUnpack High Single-Precision Floating-PointUnpacks the high-order single-precision floating-point values in the first and second source operandsand packs them into interleaved doublewords in the destination (first source). The low-orderquadwords of the source operands are ignored. The first source/destination operand is an XMMregister. The second source operand is another XMM register or 128-bit memory location.The UNPCKHPS instruction is an SSE instruction. The presence of this instruction set is indicated bya CPUID feature bit.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
