Volume 4 128-Bit Media Instructions (794098), страница 52
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(See “CPUID” in Volume 3.)MnemonicOpcodeUNPCKHPS xmm1, xmm2/mem128DescriptionUnpacks high-order single-precision floating-pointvalues in an XMM register and another XMM registeror 128-bit memory location and packs them into thedestination XMM register.0F 15 /rxmm112796 95xmm2/mem12864 63copy0127copy12796 95copy96 9564 6364 630copy32 310unpckhps.epsRelated InstructionsUNPCKHPD, UNPCKLPD, UNPCKLPSrFLAGS AffectedNoneMXCSR Flags AffectedNone405AMD64 Technology26568—Rev. 3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX40626568—Rev.
3.09—July 2007UNPCKLPDAMD64 TechnologyUnpack Low Double-Precision Floating-PointUnpacks the low-order double-precision floating-point values in the first and second source operandsand packs them into the destination (first source). The value from the first source operand is packedinto the low-order quadword of the destination, and the value from the second source operand ispacked into the high-order quadword of the destination. The high-order quadwords of the sourceoperands are ignored. The first source/destination operand is an XMM register. The second sourceoperand is another XMM register or 128-bit memory location.The UNPCKLPD instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeUNPCKLPD xmm1, xmm2/mem128Description66 0F 14 /rUnpacks low-order double-precision floating-pointvalues in an XMM register and another XMMregister or 128-bit memory location and packsthem into the destination XMM register.xmm1127xmm2/mem12864 63012764 63copy1270copy64 630unpcklpd.epsRelated InstructionsUNPCKHPD, UNPCKHPS, UNPCKLPSrFLAGS AffectedNoneMXCSR Flags AffectedNone407AMD64 Technology26568—Rev. 3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX40826568—Rev.
3.09—July 2007UNPCKLPSAMD64 TechnologyUnpack Low Single-Precision Floating-PointUnpacks the low-order single-precision floating-point values in the first and second source operandsand packs them into interleaved doublewords in the destination (first source). The high-orderquadwords of the source operands are ignored. The first source/destination operand is an XMMregister. The second source operand is another XMM register or 128-bit memory location.The UNPCKLPS instruction is an SSE instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeUNPCKLPS xmm1, xmm2/mem128DescriptionUnpacks low-order single-precision floating-pointvalues in an XMM register and another XMM registeror 128-bit memory location and packs them into thedestination XMM register.0F 14 /rxmm1127xmm2/mem12864 6332 31copy1270127copy96 9564 6332 31064 6332 31copycopy0unpcklps.epsRelated InstructionsUNPCKHPD, UNPCKHPS, UNPCKLPDrFLAGS AffectedNoneMXCSR Flags AffectedNone409AMD64 Technology26568—Rev. 3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX41026568—Rev.
3.09—July 2007XORPDAMD64 TechnologyLogical Bitwise Exclusive ORPacked Double-Precision Floating-PointPerforms a bitwise logical Exclusive OR of the two packed double-precision floating-point values inthe first source operand and the corresponding two packed double-precision floating-point values inthe second source operand and writes the result in the destination (first source). The firstsource/destination operand is an XMM register. The second source operand is another XMM registeror 128-bit memory location.The XORPD instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeXORPD xmm1, xmm2/mem12866 0F 57 /rDescriptionPerforms bitwise logical XOR of two packed doubleprecision floating-point values in an XMM register and inanother XMM register or 128-bit memory location andwrites the result in the destination XMM register.xmm1127xmm2/mem12864 63012764 630XORXORxorpd.epsRelated InstructionsANDNPD, ANDNPS, ANDPD, ANDPS, ORPD, ORPS, XORPSrFLAGS AffectedNoneMXCSR Flags AffectedNone411AMD64 Technology26568—Rev. 3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection,#GPX41226568—Rev.
3.09—July 2007AMD64 TechnologyXORPSLogical Bitwise Exclusive ORPacked Single-Precision Floating-PointPerforms a bitwise Exclusive OR of the four packed single-precision floating-point values in the firstsource operand and the corresponding four packed single-precision floating-point values in the secondsource operand and writes the result in the destination (first source). The first source/destinationoperand is an XMM register. The second source operand is another XMM register or 128-bit memorylocation.The XORPS instruction is an SSE instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeXORPS xmm1,xmm2/mem1280F 57 /rDescriptionPerforms bitwise logical XOR of four packed single-precisionfloating-point values in an XMM register and in another XMMregister or 128-bit memory location and writes the result inthe destination XMM register.xmm112796 95xmm2/mem12864 6332 31012796 9564 6332 310XORXORXORXORxorps.epsRelated InstructionsANDNPD, ANDNPS, ANDPD, ANDPS, ORPD, ORPS, XORPDrFLAGS AffectedNoneMXCSR Flags AffectedNone413AMD64 Technology26568—Rev. 3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded the data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection,#GPX41426568—Rev.
3.09—July 2007AMD64 TechnologyIndexNumerics16-bit mode ............................................................ xiv32-bit mode ............................................................ xiv64-bit mode ............................................................. xvAADDPD .................................................................... 3ADDPS ..................................................................... 6addressingRIP-relative .......................................................... xxADDSD ....................................................................
9ADDSS ................................................................... 12ADDSUBPD ........................................................... 15ADDSUBPS............................................................ 18ANDNPD ............................................................... 21ANDNPS ................................................................ 23ANDPD .................................................................. 25ANDPS ................................................................... 27Bbiased exponent ....................................................... xvCCMPPD ..................................................................CMPPS ...................................................................CMPSD ..................................................................CMPSS ...................................................................COMISD ................................................................COMISS .................................................................commit ...................................................................compatibility mode ..................................................CVTDQ2PD............................................................CVTDQ2PS ............................................................CVTPD2DQ............................................................CVTPD2PI..............................................................CVTPD2PS .............................................................CVTPI2PD..............................................................CVTPI2PS ..............................................................CVTPS2DQ ............................................................CVTPS2PD .............................................................CVTPS2PI ..............................................................CVTSD2SI..............................................................CVTSD2SS .............................................................CVTSI2SD..............................................................CVTSI2SS ..............................................................CVTSS2SD .............................................................CVTSS2SI ..............................................................Index293336394245xvxv48505254576062646668707376788082CVTTPD2DQ ..........................................................CVTTPD2PI............................................................CVTTPS2DQ ..........................................................CVTTPS2PI ............................................................CVTTSD2SI............................................................CVTTSS2SI ............................................................858790929497Ddirect referencing .....................................................
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