Volume 3 General-Purpose and System Instructions (794097), страница 67
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3.13—July 2007Table B-3 lists instructions that are reassigned to different functions in 64-bit mode. Attempted use ofthese instructions generates the reassigned function.Table B-3. Reassigned Instructions in 64-Bit ModeMnemonicOpcode(hex)Description63Opcode for MOVSXD instruction in 64-bitmode. In all other modes, this is the AdjustRequestor Privilege Level instruction opcode.40-4FREX prefixes in 64-bit mode. In all othermodes, decrement by 1 and increment by 1.ARPLDEC and INCTable B-4 lists instructions that are illegal in long mode.
Attempted use of these instructions generatesan invalid-opcode exception (#UD).Table B-4. Invalid Instructions in Long ModeOpcode(hex)MnemonicB.4DescriptionSYSENTER0F 34System CallSYSEXIT0F 35System ReturnInstructions with 64-Bit Default Operand SizeIn 64-bit mode, two groups of instructions default to 64-bit operand size without the need for a REXprefix:••Near branches —CALL, Jcc, JrCX, JMP, LOOP, and RET.All instructions, except far branches, that implicitly reference the RSP—CALL, ENTER, LEAVE,POP, PUSH, and RET (CALL and RET are in both groups of instructions).Table B-5 lists these instructions.Table B-5.
Instructions Defaulting to 64-Bit Operand SizeOpcode(hex)ImplicitlyReferenceRSPE8, FF /2yesCall Procedure NearC8yesCreate Procedure Stack FrameJccmanynoJump Conditional NearJMPE9, EB, FF /4noJump NearLEAVEC9yesDelete Procedure Stack FrameLOOPE2noLoopMnemonicCALLENTER400DescriptionGeneral-Purpose Instructions in 64-Bit Mode24594—Rev. 3.13—July 2007AMD64 TechnologyTable B-5. Instructions Defaulting to 64-Bit Operand Size (continued)Opcode(hex)ImplicitlyReferenceRSPE0, E1noLoop ConditionalPOP reg/mem8F /0yesPop Stack (register or memory)POP reg58-5FyesPop Stack (register)POP FS0F A1yesPop Stack into FS Segment RegisterPOP GS0F A9yesPop Stack into GS Segment RegisterPOPF, POPFD, POPFQ9DyesPop to rFLAGS Word, Doubleword, or QuadwordPUSH imm86AyesPush onto Stack (sign-extended byte)PUSH imm3268yesPush onto Stack (sign-extended doubleword)PUSH reg/memFF /6yesPush onto Stack (register or memory)PUSH reg50-57yesPush onto Stack (register)PUSH FS0F A0yesPush FS Segment Register onto StackPUSH GS0F A8yesPush GS Segment Register onto Stack9CyesPush rFLAGS Word, Doubleword, or Quadword ontoStackC2, C3yesReturn From Call (near)MnemonicLOOPccPUSHF, PUSHFD, PUSHFQRETDescriptionThe 64-bit default operand size can be overridden to 16 bits using the 66h operand-size override.However, it is not possible to override the operand size to 32 bits because there is no 32-bit operandsize override prefix for 64-bit mode.
See “Operand-Size Override Prefix” on page 4 for details.B.5Single-Byte INC and DEC Instructions in 64-Bit ModeIn 64-bit mode, the legacy encodings for the 16 single-byte INC and DEC instructions (one for each ofthe eight GPRs) are used to encode the REX prefix values, as described in “REX Prefixes” on page 11.Therefore, these single-byte opcodes for INC and DEC are not available in 64-bit mode, although theyare available in legacy and compatibility modes. The functionality of these INC and DEC instructionsis still available in 64-bit mode, however, using the ModRM forms of those instructions (opcodes FF/0and FF/1).B.6NOP in 64-Bit ModePrograms written for the legacy x86 architecture commonly use opcode 90h (the XCHG EAX, EAXinstruction) as a one-byte NOP.
In 64-bit mode, the processor treats opcode 90h specially in order topreserve this legacy NOP use. Without special handling in 64-bit mode, the instruction would not be atrue no-operation. Therefore, in 64-bit mode the processor treats XCHG EAX, EAX as a true NOP,regardless of operand size.General-Purpose Instructions in 64-Bit Mode401AMD64 Technology24594—Rev. 3.13—July 2007This special handling does not apply to the two-byte ModRM form of the XCHG instruction.
Unless a64-bit operand size is specified using a REX prefix byte, using the two byte form of XCHG toexchange a register with itself will not result in a no-operation because the default operation size is 32bits in 64-bit mode.B.7Segment Override Prefixes in 64-Bit ModeIn 64-bit mode, the CS, DS, ES, SS segment-override prefixes have no effect. These four prefixes areno longer treated as segment-override prefixes in the context of multiple-prefix rules. Instead, they aretreated as null prefixes.The FS and GS segment-override prefixes are treated as true segment-override prefixes in 64-bit mode.Use of the FS and GS prefixes cause their respective segment bases to be added to the effective addresscalculation.
See “FS and GS Registers in 64-Bit Mode” in Volume 2 for details.402General-Purpose Instructions in 64-Bit Mode24594—Rev. 3.13—July 2007AMD64 TechnologyAppendix C Differences Between Long Mode andLegacy ModeTable C-1 summarizes the major differences between 64-bit mode and legacy protected mode. Thethird column indicates differences between 64-bit mode and legacy mode. The fourth column indicateswhether that difference also applies to compatibility mode.Table C-1. Differences Between Long Mode and Legacy ModeTypeSubjectAddressing64-Bit Mode DifferenceApplies ToCompatibilityMode?RIP-relative addressing availableDefault data size is 32 bitsData and AddressSizesREX Prefix toggles data size to 64 bitsDefault address size is 64 bitsnoAddress size prefix toggles address size to 32 bitsVarious opcodes are invalid or changed in 64-bitmode (see Table B-2 on page 399 and Table B-3 onpage 400)ApplicationProgrammingVarious opcodes are invalid in long mode (seeTable B-4 on page 400)InstructionDifferencesyesMOV reg,imm32 becomes MOV reg,imm64 (withREX operand size prefix)REX is always enabledDirect-offset forms of MOV to or from accumulatorbecome 64-bit offsetsnoMOVD extended to MOV 64 bits between MMXregisters and long GPRs (with REX operand-sizeprefix)Differences Between Long Mode and Legacy Mode403AMD64 Technology24594—Rev.
3.13—July 2007Table C-1. Differences Between Long Mode and Legacy Mode (continued)TypeSubject64-Bit Mode DifferenceApplies ToCompatibilityMode?x86 ModesReal and virtual-8086 modes not supportedyesTask SwitchingTask switching not supportedyes64-bit virtual addressesAddressing4-level paging structuresyesPAE must always be enabledCS, DS, ES, SS segment bases are ignoredSegmentationCS, DS, ES, FS, GS, SS segment limits are ignorednoCS, DS, ES, SS Segment prefixes are ignoredAll pushes are 8 bytes16-bit interrupt and trap gates are illegalSystemProgrammingException andInterrupt Handling32-bit interrupt and trap gates are redefined as 64-bitgates and are expanded to 16 bytesyesSS is set to null on stack switchSS:RSP is pushed unconditionallyAll pushes are 8 bytes16-bit call gates are illegalCall Gates32-bit call gate type is redefined as 64-bit call gateand is expanded to 16 bytes.yesSS is set to null on stack switchSystem-DescriptorRegistersGDT, IDT, LDT, TR base registers expanded to 64bitsSystem-Descriptor LGDT and LIDT use expanded 10-byte pseudodescriptors.Table Entries andPseudo-descriptors LLDT and LTR use expanded 16-byte table entries.404yesnoDifferences Between Long Mode and Legacy Mode24594—Rev.
3.13—July 2007AMD64 TechnologyAppendix D Instruction Subsets and CPUIDFeature SetsTable D-1 is an alphabetical list of the AMD64 instruction set, including the instructions from all fiveof the instruction subsets that make up the entire AMD64 instruction-set architecture:•••••Chapter 3, “General-Purpose Instruction Reference.”Chapter 4, “System Instruction Reference.”“128-Bit Media Instruction Reference” in Volume 4.“64-Bit Media Instruction Reference” in Volume 5.“x87 Floating-Point Instruction Reference” in Volume 5.Several instructions belong to—and are described in—multiple instruction subsets.
Table D-1 showsthe minimum current privilege level (CPL) required to execute each instruction and the instructionsubset(s) to which the instruction belongs. For each instruction subset, the CPUID feature set(s) thatenables the instruction is shown.D.1Instruction SubsetsFigure D-1 on page 406 shows the relationship between the five instruction subsets and the CPUIDfeature sets. Dashed-line polygons represent the instruction subsets. Circles represent the majorCPUID feature sets that enable various classes of instructions.
(There are a few additional CPUIDfeature sets, not shown, each of which apply to only a few instructions.)The overlapping of the 128-bit and 64-bit media instruction subsets indicates that these subsets sharesome common mnemonics. However, these common mnemonics either have distinct opcodes for eachsubset or they take operands in both the MMX and XMM register sets.The horizontal axis of Figure D-1 shows how the subsets and CPUID feature sets have evolved overtime.Instruction Subsets and CPUID Feature Sets405AMD64 Technology24594—Rev. 3.13—July 2007General-Purpose InstructionsLong-ModeInstructionsInstructionsBasicSystem InstructionsSVMInstructionsx87 Instructionsx87 InstructionsSSE3InstructionsAMD Extensionsto MMX™InstructionsMMX™InstructionsSSEInstructions64-Bit MediaInstructionsAMD 3DNow!™Instructions128-Bit MediaInstructionsAMD Extensionto3DNow!™InstructionsTime of IntroductionSSE2InstructionsSSE4AInstructionsDashed-line boxes show instruction subsets.Circles show major CPUID feature sets.(Minor features sets are not shown.)Figure D-1.406Instruction Subsets vs.
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