Volume 3 General-Purpose and System Instructions (794097), страница 64
Текст из файла (страница 64)
is sign-extendedto 64 bits.C7B8 through BFA1 (moffset)Promoted to64 bits.Zero-extends 32bit registerresults to 64 bits.Memory offsetsare addresssized and defaultto 64 bits.A3 (moffset)MOV—Move to/from Segment Registers8C8EMOV(CRn)—Move to/from ControlRegisters0F 2232 bits0F 210F 23Memory offsetsare addresssized and defaultto 64 bits.Zero-extends 32-bit register resultsto 64 bits.Same aslegacy mode.
Operand sizefixed at 16No GPR register results.bits.Promoted to64 bits.The high 32 bits of control registersOperand sizediffer in their writability and reservedfixed at 64status. See “System Resources” inbits.Volume 2 for details.Promoted to64 bits.The high 32 bits of debug registersOperand size differ in their writability and reservedfixed at 64 status.
See “Debug andPerformance Resources” inbits.Volume 2 for details.0F 20MOV(DRn)—Move to/from DebugRegisters64-bit immediate.32 bitsNote:1. See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions.
Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.386General-Purpose Instructions in 64-Bit Mode24594—Rev.
3.13—July 2007AMD64 TechnologyTable B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1Type ofOperation2DefaultOperandSize3MOVD—Move Doubleword or Quadword66 0F 6EPromoted to64 bits.32 bitsPromoted to64 bits.32 bitsNo GPR register results.32 bitsMOVSD: MoveStringDoublewords.66 0F 7EMOVNTI—Move Non-TemporalDoubleword0F C3MOVS, MOVSW, MOVSD, MOVSQ—Move StringA5For 64-BitOperand Size4Zero-extends 32bit registerresults to 64 bits.0F 6E0F 7EFor 32-BitOperand Size4Promoted to64 bits.Zero-extends 32bit registerresults to 128bits.See footnote5Zero-extends 64bit registerresults to 128bits.MOVSQ (newmnemonic):Move StringQuadwords.See footnote5MOVSX—Move with Sign-Extend0F BEPromoted to64 bits.0F BF32 bitsSign-extendsZero-extends 32- byte tobit registerquadword.results to 64 bits.
Sign-extendsword toquadword.Note:1. See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3.
If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged.
Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.General-Purpose Instructions in 64-Bit Mode387AMD64 Technology24594—Rev.
3.13—July 2007Table B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1MOVSXD—Move with Sign-ExtendDoubleword63Type ofOperation2DefaultOperandSize3Newinstruction,available onlyin 64-bitmode. (Inother modes,this opcodeis ARPLinstruction.)32 bitsZero-extends 32- Sign-extendsbit registerdoubleword toresults to 64 bits. quadword.32 bitsZero-extendsZero-extends 32- byte toquadword.bit registerresults to 64 bits. Zero-extendsword toquadword.32 bitsRDX:RAX=RAX *Zero-extends 32quadword inbit registerregister orresults to 64 bits.memory.For 32-BitOperand Size4For 64-BitOperand Size4MOVZX—Move with Zero-Extend0F B6Promoted to64 bits.0F B7MUL—Multiply UnsignedF7 /4MWAIT—Monitor Wait0F 01 C9NEG—Negate Two’s ComplementF7 /3NOP—No Operation90NOT—Negate One’s ComplementF7 /2Promoted to64 bits.Operand sizeSame asfixed at 32No GPR register results.legacy mode.bits.Promoted to64 bits.Same aslegacy mode.Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.Not relevant.
No GPR register results.32 bitsZero-extends 32bit registerresults to 64 bits.Note:1. See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3.
If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5.
Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.388General-Purpose Instructions in 64-Bit Mode24594—Rev.
3.13—July 2007AMD64 TechnologyTable B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1Type ofOperation2DefaultOperandSize3For 32-BitOperand Size4Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.Same aslegacy mode.32 bitsNo GPR register results.32 bitsWrites doubleword to I/O port.No GPR register results.For 64-BitOperand Size4OR—Logical OR090B0D81 /183 /1OUT—Output to PortE7EFOUTS, OUTSW, OUTSD—Output String6FPAUSE—PauseF3 90Same aslegacy mode.Same aslegacy mode.See footnote5Not relevant. No GPR register results.POP—Pop Stack8F /0Promoted to64 bits.64 bitsCannot encode6No GPR registerresults.Same aslegacy mode.64 bitsCannot encode6No GPR registerresults.58 through 5FPOP—Pop (segment register from)Stack0F A1 (POP FS)0F A9 (POP GS)1F (POP DS)07 (POP ES)INVALID IN 64-BIT MODE (invalid-opcode exception)17 (POP SS)Note:1.
See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits.
If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.General-Purpose Instructions in 64-Bit Mode389AMD64 Technology24594—Rev.
3.13—July 2007Table B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1POPA, POPAD—Pop All to GPR Wordsor DoublewordsType ofOperation2DefaultOperandSize3For 32-BitOperand Size4For 64-BitOperand Size4INVALID IN 64-BIT MODE (invalid-opcode exception)61POPCNT—Bit Population CountF3 0F B8Promoted to64 bits.32 bitsZero-extends 32-bit register resultsto 64 bits.POPF, POPFD, POPFQ—Pop torFLAGS Word, Doublword, or Quadword9DPREFETCH—Prefetch L1 Data-CacheLine0F 0D /0PREFETCHlevel—Prefetch Data toCache Level level0F 18 /0-3Promoted to64 bits.Same aslegacy mode.64 bitsCannot encode6POPFQ (newmnemonic): Pops64 bits off stack,writes low 32 bitsinto EFLAGS andzero-extends thehigh 32 bits ofRFLAGS.Not relevant.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
