Volume 3 General-Purpose and System Instructions (794097), страница 68
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CPUID Feature SetsInstruction Subsets and CPUID Feature Sets24594—Rev. 3.13—July 2007D.2AMD64 TechnologyCPUID Feature SetsThe CPUID feature sets shown in Figure D-1 and listed in Table D-1 on page 409 include:•••••Basic Instructions—Instructions that are supported in all hardware implementations of theAMD64 architecture, except that the following instructions are implemented only if theirassociated CPUID function bit is set:- CLFLUSH, indicated by EDX bit 19 of CPUID function 0000_0001h.- CMPXCHG8B, indicated by EDX bit 8 of CPUID function 0000_0001h and function8000_0001h.- CMPXCHG16B, indicated by ECX bit 13 of CPUID function 0000_0001h.- CMOVcc (conditional moves), indicated by EDX bit 15 of CPUID function 0000_0001h andfunction 8000_0001h.- RDMSR and WRMSR, indicated by EDX bit 5 of CPUID function 0000_0001h and function8000_0001h.- RDTSC, indicated by EDX bit 4 of CPUID function 0000_0001h and function 8000_0001h.- RDTSCP, indicated by EDX bit 27 of CPUID function 8000_0001h.- SYSCALL and SYSRET, indicated by EDX bit 11 of CPUID function 8000_0001h.- SYSENTER and SYSEXIT, indicated by EDX bit 11 of CPUID function 0000_0001h.x87 Instructions—Legacy floating-point instructions that use the ST(0)–ST(7) stack registers(FPR0–FPR7 physical registers) and are supported if the following bits are set:- On-chip floating-point unit, indicated by EDX bit 0 of CPUID function 0000_0001h andfunction 8000_0001h.- FCMOVcc (conditional moves), indicated by EDX bit 15 of CPUID function 0000_0001h andfunction 8000_0001h.
This bit indicates support for x87 floating-point conditional moves(FCMOVcc) whenever the On-Chip Floating-Point Unit bit (bit 0) is also set.MMX™ Instructions—Vector integer instructions that are implemented in the MMX instructionset, use the MMX logical registers (FPR0–FPR7 physical registers), and are supported if thefollowing bit is set:- MMX instructions, indicated by EDX bit 23 of CPUID function 0000_0001h and function8000_0001h.AMD 3DNow!™ Instructions—Vector floating-point instructions that comprise the AMD3DNow! technology, use the MMX logical registers (FPR0–FPR7 physical registers), and aresupported if the following bit is set:- AMD 3DNow! instructions, indicated by EDX bit 31 of CPUID function 8000_0001h.AMD Extensions to MMX™ Instructions—Vector integer instructions that use the MMX registersand are supported if the following bit is set:- AMD extensions to MMX instructions, indicated by EDX bit 22 of CPUID function8000_0001h.Instruction Subsets and CPUID Feature Sets407AMD64 Technology•••••••24594—Rev.
3.13—July 2007AMD Extensions to 3DNow!™ Instructions—Vector floating-point instructions that use the MMXregisters and are supported if the following bit is set:- AMD extensions to 3DNow! instructions, indicated by EDX bit 30 of CPUID function8000_0001h.SSE Instructions—Vector integer instructions that use the MMX registers, single-precision vectorand scalar floating-point instructions that use the XMM registers, plus other instructions for datatype conversion, prefetching, cache control, and memory-access ordering. These instructions aresupported if the following bits are set:- SSE, indicated by EDX bit 25 of CPUID function 0000_0001h.- FXSAVE and FXRSTOR, indicated by EDX bit 24 of CPUID function 0000_0001h andfunction 8000_0001h.Several SSE opcodes are also implemented by the AMD Extensions to MMX™ Instructions.SSE2 Instructions—Vector and scalar integer and double-precision floating-point instructions thatuse the XMM registers, plus other instructions for data-type conversion, cache control, andmemory-access ordering.
These instructions are supported if the following bit is set:- SSE2, indicated by EDX bit 26 of CPUID function 0000_0001h.Several instructions originally implemented as MMX™ instructions are extended in the SSE2instruction set to include opcodes that use XMM registers.SSE3 Instructions—Horizontal addition and subtraction of packed single-precision and doubleprecision floating point values, simultaneous addition and subtraction of packed single-precisionand double-precision values, move with duplication, and floating-point-to-integer conversion.These instructions are supported if the following bit is set:- SSE3, indicated by ECX bit 0 of CPUID function 0000_0001h.SSE4A Instructions—The SSE4A instructions are EXTRQ, INSERTQ, MOVNTSD, andMOVNTSS.- SSE4A, indicated by ECX bit 6 of CPUID function 8000_0001h.Long-Mode Instructions—Instructions introduced by AMD with the AMD64 architecture.
Theseinstructions are supported if the following bit is set:- Long mode, indicated by EDX bit 29 of CPUID function 8000_0001h.SVM Instructions—Instructions introduced by AMD with the Secure Virtual Machine feature.These instructions are supported if the following bit is set:- SVM, indicated by ECX bit 2 of CPUID function 8000_0001h.For complete details on the CPUID feature sets listed in Table D-1, see the AMD CPUIDSpecification, order# 25481.408Instruction Subsets and CPUID Feature Sets24594—Rev. 3.13—July 2007D.3Table D-1.AMD64 TechnologyInstruction ListInstruction Subsets and CPUID Feature SetsInstruction Subsetand CPUID Feature Set(s)1InstructionDescriptionCPLGeneralPurposeAAAASCII Adjust After Addition3BasicAADASCII Adjust BeforeDivision3BasicAAMASCII Adjust After Multiply3BasicAASASCII Adjust AfterSubtraction3BasicADCAdd with Carry3BasicADDSigned or Unsigned Add3BasicADDPDAdd Packed DoublePrecision Floating-Point3SSE2ADDPSAdd Packed SinglePrecision Floating-Point3SSEADDSDAdd Scalar DoublePrecision Floating-Point3SSE2ADDSSAdd Scalar SinglePrecision Floating-Point3SSEADDSUBPDAdd and Subtract DoublePrecision3SSE3ADDSUBPSAdd and Subtract SinglePrecision3SSE3ANDLogical AND3ANDNPDLogical Bitwise AND NOTPacked Double-PrecisionFloating-Point3SSE2ANDNPSLogical Bitwise AND NOTPacked Single-PrecisionFloating-Point3SSEANDPDLogical Bitwise ANDPacked Double-PrecisionFloating-Point3SSE2ANDPSLogical Bitwise ANDPacked Single-PrecisionFloating-Point3SSEARPLAdjust Requestor PrivilegeLevel3BOUNDCheck Array Bounds3Mnemonic128-BitMedia64-BitMediax87SystemBasicBasicBasicNote:1.
Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Instruction Subsets and CPUID Feature Sets409AMD64 TechnologyTable D-1.24594—Rev. 3.13—July 2007Instruction Subsets and CPUID Feature Sets (continued)Instruction Subsetand CPUID Feature Set(s)1InstructionMnemonicDescriptionCPLGeneralPurpose3BasicBSFBit Scan ForwardBSRBit Scan Reverse3BasicBSWAPByte Swap3BasicBTBit Test3BasicBTCBit Test and Complement3BasicBTRBit Test and Reset3BasicBTSBit Test and Set3BasicCALLProcedure Call3BasicCBWConvert Byte to Word3BasicCDQConvert Doubleword toQuadword3BasicCDQEConvert Doubleword toQuadword3Long ModeCLCClear Carry Flag3BasicCLDClear Direction Flag3BasicCLFLUSH128-BitMedia64-BitMediax87SystemCLFLUSHCache Line Flush3CLGIClear Global Interrupt Flag0SVMCLIClear Interrupt Flag3BasicCLTSClear Task-Switched Flagin CR00BasicCMCComplement Carry Flag3BasicCMOVccConditional Move3CMOVccCMPCompare3BasicCMPPDCompare Packed DoublePrecision Floating-Point3SSE2CMPPSCompare Packed SinglePrecision Floating-Point3SSECMPSCompare Strings3BasicCMPSBCompare Strings by Byte3BasicCMPSDCompare Strings byDoubleword3Basic2CMPSDCompare Scalar DoublePrecision Floating-Point3CMPSQCompare Strings byQuadword3CMPSSCompare Scalar SinglePrecision Floating-Point3SSE22Long ModeSSENote:1.
Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.410Instruction Subsets and CPUID Feature Sets24594—Rev. 3.13—July 2007Table D-1.AMD64 TechnologyInstruction Subsets and CPUID Feature Sets (continued)Instruction Subsetand CPUID Feature Set(s)1InstructionMnemonicDescriptionCPLGeneralPurpose128-BitMediaCMPSWCompare Strings by Word3BasicCMPXCHGCompare and Exchange3BasicCMPXCHG8BCompare and ExchangeEight Bytes3CMPXCHG8BCMPXCHG16BCompare and ExchangeSixteen Bytes3CMPXCHG16BCOMISDCompare Ordered ScalarDouble-Precision FloatingPoint3SSE2COMISSCompare Ordered ScalarSingle-Precision FloatingPoint3SSECPUIDProcessor Identification3BasicCQOConvert Quadword toDouble Quadword3Long ModeCVTDQ2PDConvert PackedDoubleword Integers toPacked Double-PrecisionFloating-Point3SSE2CVTDQ2PSConvert PackedDoubleword Integers toPacked Single-PrecisionFloating-Point3SSE2CVTPD2DQConvert Packed DoublePrecision Floating-Point toPacked DoublewordIntegers3SSE2CVTPD2PIConvert Packed DoublePrecision Floating-Point toPacked DoublewordIntegers3SSE2CVTPD2PSConvert Packed DoublePrecision Floating-Point toPacked Single-PrecisionFloating-Point3SSE2CVTPI2PDConvert PackedDoubleword Integers toPacked Double-PrecisionFloating-Point3SSE264-BitMediax87SystemSSE2SSE2Note:1.
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