Volume 3 General-Purpose and System Instructions (794097), страница 70
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Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Instruction Subsets and CPUID Feature Sets419AMD64 TechnologyTable D-1.24594—Rev. 3.13—July 2007Instruction Subsets and CPUID Feature Sets (continued)Instruction Subsetand CPUID Feature Set(s)1InstructionCPLGeneralPurposeLoad DS Far Pointer3BasicLEALoad Effective Address3BasicLEAVEDelete Procedure StackFrame3BasicMnemonicLDSDescription128-BitMedia64-BitMediax87SystemLESLoad ES Far Pointer3BasicLFENCELoad Fence3SSE2LFSLoad FS Far Pointer3BasicLGDTLoad Global DescriptorTable Register0LGSLoad GS Far Pointer3LIDTLoad Interrupt DescriptorTable Register0BasicLLDTLoad Local DescriptorTable Register0BasicLMSWLoad Machine Status Word0BasicLODSLoad String3BasicLODSBLoad String Byte3BasicBasicBasicLODSDLoad String Doubleword3BasicLODSQLoad String Quadword3Long ModeLODSWLoad String Word3BasicLOOPLoop3BasicLOOPELoop if Equal3BasicLOOPNELoop if Not Equal3BasicLOOPNZLoop if Not Zero3BasicLOOPZLoop if Zero3BasicLSLLoad Segment Limit3BasicLSSLoad SS Segment Register3BasicLTRLoad Task Register0LZCNTCount Leading Zeros3MASKMOVDQUMasked Move DoubleQuadword Unaligned3MASKMOVQMasked Move Quadword3MAXPDMaximum Packed DoublePrecision Floating-Point3BasicBasicSSE2SSE, MMXExtensionsSSE2Note:1.
Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.420Instruction Subsets and CPUID Feature Sets24594—Rev.
3.13—July 2007Table D-1.AMD64 TechnologyInstruction Subsets and CPUID Feature Sets (continued)Instruction Subsetand CPUID Feature Set(s)1InstructionMnemonicDescriptionCPLGeneralPurpose128-BitMedia64-BitMediax87SystemMAXPSMaximum Packed SinglePrecision Floating-Point3SSEMAXSDMaximum Scalar DoublePrecision Floating-Point3SSE2MAXSSMaximum Scalar SinglePrecision Floating-Point3SSEMFENCEMemory Fence3MINPDMinimum Packed DoublePrecision Floating-Point3SSE2MINPSMinimum Packed SinglePrecision Floating-Point3SSEMINSDMinimum Scalar DoublePrecision Floating-Point3SSE2MINSSMinimum Scalar SinglePrecision Floating-Point3SSEMONITORSetup Monitor Address0MOVMove3MOV CRnMove to/from ControlRegisters0BasicMOV DRnMove to/from DebugRegisters0BasicMOVAPDMove Aligned PackedDouble-Precision FloatingPoint3SSE2MOVAPSMove Aligned PackedSingle-Precision FloatingPoint3SSEMOVDMove Doubleword orQuadword3MOVDDUPMove Double-Precisionand Duplicate3SSE3MOVDQ2QMove Quadword toQuadword3SSE2MOVDQAMove Aligned DoubleQuadword3SSE2MOVDQUMove Unaligned DoubleQuadword3SSE2SSE2BasicBasicMMX, SSE2SSE2MMXSSE2Note:1.
Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Instruction Subsets and CPUID Feature Sets421AMD64 TechnologyTable D-1.24594—Rev. 3.13—July 2007Instruction Subsets and CPUID Feature Sets (continued)Instruction Subsetand CPUID Feature Set(s)1InstructionMnemonicDescriptionCPLGeneralPurpose128-BitMediaMOVHLPSMove Packed SinglePrecision Floating-PointHigh to Low3SSEMOVHPDMove High Packed DoublePrecision Floating-Point3SSE2MOVHPSMove High Packed SinglePrecision Floating-Point3SSEMOVLHPSMove Packed SinglePrecision Floating-PointLow to High3SSEMOVLPDMove Low Packed DoublePrecision Floating-Point3SSE2MOVLPSMove Low Packed SinglePrecision Floating-Point3SSEMOVMSKPDExtract Packed DoublePrecision Floating-PointSign Mask3SSE2SSE2MOVMSKPSExtract Packed SinglePrecision Floating-PointSign Mask3SSESSEMOVNTDQMove Non-TemporalDouble Quadword3MOVNTIMove Non-TemporalDoubleword or Quadword3MOVNTPDMove Non-TemporalPacked Double-PrecisionFloating-Point3SSE2MOVNTPSMove Non-TemporalPacked Single-PrecisionFloating-Point3SSEMOVNTSDMove Non-Temporal ScalarDouble-Precision FloatingPoint3SSE4AMOVNTSSMove Non-Temporal ScalarSingle-Precision FloatingPoint3SSE4AMOVNTQMove Non-TemporalQuadword3MOVQMove Quadword364-BitMediax87SystemSSE2SSE2SSE, MMXExtensionsSSE2MMXNote:1.
Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.422Instruction Subsets and CPUID Feature Sets24594—Rev. 3.13—July 2007Table D-1.AMD64 TechnologyInstruction Subsets and CPUID Feature Sets (continued)Instruction Subsetand CPUID Feature Set(s)1InstructionMnemonicDescriptionCPLGeneralPurpose128-BitMedia64-BitMediaSSE2SSE2MOVQ2DQMove Quadword toQuadwordMOVSMove String3BasicMOVSBMove String Byte3BasicMOVSDMove String Doubleword3Basic2MOVSDMove Scalar DoublePrecision Floating-Point3SSE22MOVSHDUPMove Single-PrecisionHigh and Duplicate3SSE3MOVSLDUPMove Single-Precision Lowand Duplicate3SSE3MOVSQMove String Quadword3MOVSSMove Scalar SinglePrecision Floating-Point3MOVSWMove String Word3BasicMOVSXMove with Sign-Extend3BasicMOVSXDMove with Sign-ExtendDoubleword3Long ModeMOVUPDMove Unaligned PackedDouble-Precision FloatingPoint3SSE2MOVUPSMove Unaligned PackedSingle-Precision FloatingPoint3SSEMOVZXMove with Zero-Extend3BasicMULMultiply Unsigned3BasicMULPDMultiply Packed DoublePrecision Floating-Point3SSE2MULPSMultiply Packed SinglePrecision Floating-Point3SSEMULSDMultiply Scalar DoublePrecision Floating-Point3SSE2MULSSMultiply Scalar SinglePrecision Floating-Point3SSEMWAITMonitor Wait0NEGTwo's ComplementNegation33x87SystemLong ModeSSEBasicBasicNote:1.
Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Instruction Subsets and CPUID Feature Sets423AMD64 TechnologyTable D-1.24594—Rev. 3.13—July 2007Instruction Subsets and CPUID Feature Sets (continued)Instruction Subsetand CPUID Feature Set(s)1InstructionMnemonicDescriptionCPLGeneralPurpose128-BitMedia64-BitMediaNOPNo Operation3BasicNOTOne's ComplementNegation3BasicORLogical OR3BasicORPDLogical Bitwise OR PackedDouble-Precision FloatingPoint3SSE2ORPSLogical Bitwise OR PackedSingle-Precision FloatingPoint3SSEOUTOutput to Port3BasicOUTSOutput String3BasicOUTSBOutput String Byte3BasicOUTSDOutput String Doubleword3BasicOUTSWOutput String Word3BasicPACKSSDWPack with SaturationSigned Doubleword toWord3SSE2MMXPACKSSWBPack with SaturationSigned Word to Byte3SSE2MMXPACKUSWBPack with SaturationSigned Word to UnsignedByte3SSE2MMXPADDBPacked Add Bytes3SSE2MMXPADDDPacked Add Doublewords3SSE2MMXPADDQPacked Add Quadwords3SSE2SSE2PADDSBPacked Add Signed withSaturation Bytes3SSE2MMXPADDSWPacked Add Signed withSaturation Words3SSE2MMXPADDUSBPacked Add Unsigned withSaturation Bytes3SSE2MMXPADDUSWPacked Add Unsigned withSaturation Words3SSE2MMXPADDWPacked Add Words3SSE2MMXPANDPacked Logical BitwiseAND3SSE2MMXx87SystemNote:1.
Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.424Instruction Subsets and CPUID Feature Sets24594—Rev. 3.13—July 2007Table D-1.AMD64 TechnologyInstruction Subsets and CPUID Feature Sets (continued)Instruction Subsetand CPUID Feature Set(s)1InstructionMnemonicDescriptionCPLGeneralPurpose128-BitMedia64-BitMediaPANDNPacked Logical BitwiseAND NOT3SSE2MMXPAVGBPacked Average UnsignedBytes3SSE2SSE, MMXExtensionsPAVGUSBPacked Average UnsignedBytes3PAVGWPacked Average UnsignedWords3SSE2SSE, MMXExtensionsPCMPEQBPacked Compare EqualBytes3SSE2MMXPCMPEQDPacked Compare EqualDoublewords3SSE2MMXPCMPEQWPacked Compare EqualWords3SSE2MMXPCMPGTBPacked Compare GreaterThan Signed Bytes3SSE2MMXPCMPGTDPacked Compare GreaterThan Signed Doublewords3SSE2MMXPCMPGTWPacked Compare GreaterThan Signed Words3SSE2MMXPEXTRWPacked Extract Word3SSE2SSE, MMXExtensionsPF2IDPacked Floating-Point toInteger DoublewordConversion33DNow!PF2IWPacked Floating-Point toInteger Word Conversion33DNow!ExtensionsPFACCPacked Floating-PointAccumulate33DNow!PFADDPacked Floating-Point Add33DNow!PFCMPEQPacked Floating-PointCompare Equal33DNow!PFCMPGEPacked Floating-PointCompare Greater or Equal33DNow!PFCMPGTPacked Floating-PointCompare Greater Than33DNow!PFMAXPacked Floating-PointMaximum33DNow!x87System3DNow!Note:1.
Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Instruction Subsets and CPUID Feature Sets425AMD64 TechnologyTable D-1.24594—Rev. 3.13—July 2007Instruction Subsets and CPUID Feature Sets (continued)Instruction Subsetand CPUID Feature Set(s)1InstructionMnemonicDescriptionCPLGeneralPurpose128-BitMedia64-BitMediaPFMINPacked Floating-PointMinimum33DNow!PFMULPacked Floating-PointMultiply33DNow!PFNACCPacked Floating-PointNegative Accumulate33DNow!ExtensionsPFPNACCPacked Floating-PointPositive-NegativeAccumulate33DNow!ExtensionsPFRCPPacked Floating-PointReciprocal Approximation33DNow!PFRCPIT1Packed Floating-PointReciprocal, Iteration 133DNow!PFRCPIT2Packed Floating-PointReciprocal or ReciprocalSquare Root, Iteration 233DNow!PFRSQIT1Packed Floating-PointReciprocal Square Root,Iteration 133DNow!PFRSQRTPacked Floating-PointReciprocal Square RootApproximation33DNow!PFSUBPacked Floating-PointSubtract33DNow!PFSUBRPacked Floating-PointSubtract Reverse33DNow!PI2FDPacked Integer to FloatingPoint DoublewordConversion33DNow!PI2FWPacked Integer To FloatingPoint Word Conversion33DNow!ExtensionsPINSRWPacked Insert Word3SSE2SSE, MMXExtensionsPMADDWDPacked Multiply Words andAdd Doublewords3SSE2MMXPMAXSWPacked Maximum SignedWords3SSE2SSE, MMXExtensionsx87SystemNote:1.
Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.426Instruction Subsets and CPUID Feature Sets24594—Rev. 3.13—July 2007Table D-1.AMD64 TechnologyInstruction Subsets and CPUID Feature Sets (continued)Instruction Subsetand CPUID Feature Set(s)1InstructionMnemonicDescriptionCPLGeneralPurpose128-BitMedia64-BitMediaPMAXUBPacked MaximumUnsigned Bytes3SSE2SSE, MMXExtensionsPMINSWPacked Minimum SignedWords3SSE2SSE, MMXExtensionsPMINUBPacked Minimum UnsignedBytes3SSE2SSE, MMXExtensionsPMOVMSKBPacked Move Mask Byte3SSE2SSE, MMXExtensionsPMULHRWPacked Multiply HighRounded Word3PMULHUWPacked Multiply HighUnsigned Word3SSE2SSE, MMXExtensionsPMULHWPacked Multiply HighSigned Word3SSE2MMXPMULLWPacked Multiply LowSigned Word3SSE2MMXPMULUDQPacked Multiply UnsignedDoubleword and StoreQuadword3SSE2SSE2SSE2MMXSSE2SSE, MMXExtensionsx87System3DNow!POPPop Stack3BasicPOPAPop All to GPR Words3BasicPOPADPop All to GPRDoublewords3BasicPOPCNTBit Population Count3BasicPOPFPop to FLAGS Word3BasicPOPFDPop to EFLAGSDoubleword3BasicPOPFQPop to RFLAGS Quadword3Long ModePORPacked Logical Bitwise OR3PREFETCHPrefetch L1 Data-CacheLine33DNow!™,Long ModePREFETCHlevelPrefetch Data to CacheLevel level3SSE, MMXExtensionsPREFETCHWPrefetch L1 Data-CacheLine for Write33DNow!,Long ModePSADBWPacked Sum of AbsoluteDifferences of Bytes into aWord3Note:1.
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