Volume 3 General-Purpose and System Instructions (794097), страница 71
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Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Instruction Subsets and CPUID Feature Sets427AMD64 TechnologyTable D-1.24594—Rev. 3.13—July 2007Instruction Subsets and CPUID Feature Sets (continued)Instruction Subsetand CPUID Feature Set(s)1InstructionMnemonicDescriptionCPLGeneralPurpose128-BitMedia64-BitMediaPSHUFDPacked ShuffleDoublewords3SSE2PSHUFHWPacked Shuffle High Words3SSE2PSHUFLWPacked Shuffle Low Words3SSE2PSHUFWPacked Shuffle Words3PSLLDPacked Shift Left LogicalDoublewords3SSE2PSLLDQPacked Shift Left LogicalDouble Quadword3SSE2PSLLQPacked Shift Left LogicalQuadwords3SSE2MMXPSLLWPacked Shift Left LogicalWords3SSE2MMXPSRADPacked Shift RightArithmetic Doublewords3SSE2MMXPSRAWPacked Shift RightArithmetic Words3SSE2MMXPSRLDPacked Shift Right LogicalDoublewords3SSE2MMXPSRLDQPacked Shift Right LogicalDouble Quadword3SSE2PSRLQPacked Shift Right LogicalQuadwords3SSE2MMXPSRLWPacked Shift Right LogicalWords3SSE2MMXPSUBBPacked Subtract Bytes3SSE2MMXPSUBDPacked SubtractDoublewords3SSE2MMXPSUBQPacked Subtract Quadword3SSE2SSE2PSUBSBPacked Subtract SignedWith Saturation Bytes3SSE2MMXPSUBSWPacked Subtract Signedwith Saturation Words3SSE2MMXPSUBUSBPacked Subtract Unsignedand Saturate Bytes3SSE2MMXPSUBUSWPacked Subtract Unsignedand Saturate Words3SSE2MMXx87SystemSSE, MMXExtensionsMMXNote:1.
Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.428Instruction Subsets and CPUID Feature Sets24594—Rev. 3.13—July 2007Table D-1.AMD64 TechnologyInstruction Subsets and CPUID Feature Sets (continued)Instruction Subsetand CPUID Feature Set(s)1InstructionMnemonicDescriptionCPLGeneralPurpose128-BitMedia64-BitMediaSSE2MMXPSUBWPacked Subtract Words3PSWAPDPacked Swap Doubleword3PUNPCKHBWUnpack and InterleaveHigh Bytes3SSE2MMXPUNPCKHDQUnpack and InterleaveHigh Doublewords3SSE2MMXPUNPCKHQDQUnpack and InterleaveHigh Quadwords3SSE2PUNPCKHWDUnpack and InterleaveHigh Words3SSE2MMXPUNPCKLBWUnpack and Interleave LowBytes3SSE2MMXPUNPCKLDQUnpack and Interleave LowDoublewords3SSE2MMXPUNPCKLQDQUnpack and Interleave LowQuadwords3SSE2PUNPCKLWDUnpack and Interleave LowWords3SSE23DNow!PUSHPush onto Stack3BasicPUSHAPush All GPR Words ontoStack3BasicPUSHADPush All GPRDoublewords onto Stack3BasicPUSHFPush EFLAGS Word ontoStack3BasicPUSHFDPush EFLAGS Doublewordonto Stack3BasicPUSHFQPush RFLAGS Quadwordonto Stack3Long ModePXORPacked Logical BitwiseExclusive OR3SSE2MMXRCLRotate Through Carry Left3RCPPSReciprocal Packed SinglePrecision Floating-Point3SSERCPSSReciprocal Scalar SinglePrecision Floating-Point3SSEx87System3DNow!ExtensionsBasicNote:1.
Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Instruction Subsets and CPUID Feature Sets429AMD64 TechnologyTable D-1.24594—Rev.
3.13—July 2007Instruction Subsets and CPUID Feature Sets (continued)Instruction Subsetand CPUID Feature Set(s)1InstructionMnemonicDescriptionCPLGeneralPurposeBasic128-BitMedia64-BitMediax87SystemRCRRotate Through CarryRight3RDMSRRead Model-SpecificRegister0RDMSR,WRMSRRDPMCRead PerformanceMonitoring Counter3BasicRDTSCRead Time-Stamp Counter3TSCRDTSCPRead Time-Stamp Counterand Processor ID3RDTSCPRETReturn from Call3BasicROLRotate Left3BasicRORRotate Right3BasicRSMResume from SystemManagement Mode3RSQRTPSReciprocal Square RootPacked Single-PrecisionFloating-Point3SSERSQRTSSReciprocal Square RootScalar Single-PrecisionFloating-Point3SSESAHFStore AH into Flags3BasicSALShift Arithmetic Left3BasicSARShift Arithmetic Right3BasicSBBSubtract with Borrow3BasicSCASScan String3BasicSCASBScan String as Bytes3BasicSCASDScan String as Doubleword3BasicSCASQScan String as Quadword3Long ModeSCASWScan String as Words3BasicSETccSet Byte if Condition3BasicSFENCEStore Fence3SSE,MMX™ExtensionsSGDTStore Global DescriptorTable Register3SHLShift Left3BasicSHLDShift Left Double3BasicBasicBasicNote:1.
Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.430Instruction Subsets and CPUID Feature Sets24594—Rev. 3.13—July 2007Table D-1.AMD64 TechnologyInstruction Subsets and CPUID Feature Sets (continued)Instruction Subsetand CPUID Feature Set(s)1InstructionCPLGeneralPurposeShift Right3BasicSHRDShift Right Double3BasicSHUFPDShuffle Packed DoublePrecision Floating-Point3SSE2SHUFPSShuffle Packed SinglePrecision Floating-Point3SSESIDTStore Interrupt DescriptorTable Register3BasicSKINITSecure Init and Jump withAttestation0SVMSLDTStore Local DescriptorTable Register3BasicSMSWStore Machine StatusWord3BasicSQRTPDSquare Root PackedDouble-Precision FloatingPoint3SSE2SQRTPSSquare Root PackedSingle-Precision FloatingPoint3SSESQRTSDSquare Root ScalarDouble-Precision FloatingPoint3SSE2SQRTSSSquare Root Scalar SinglePrecision Floating-Point3SSESTCSet Carry Flag3BasicSTDSet Direction Flag3BasicSTGISet Global Interrupt Flag0SVMSTISet Interrupt Flag3BasicSTMXCSRStore MXCSRControl/Status Register3STOSStore String3BasicSTOSBStore String Bytes3BasicMnemonicSHRDescription128-BitMedia64-BitMediax87SystemSSESTOSDStore String Doublewords3BasicSTOSQStore String Quadwords3Long ModeSTOSWStore String Words3BasicSTRStore Task Register3BasicNote:1.
Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Instruction Subsets and CPUID Feature Sets431AMD64 TechnologyTable D-1.24594—Rev. 3.13—July 2007Instruction Subsets and CPUID Feature Sets (continued)Instruction Subsetand CPUID Feature Set(s)1InstructionMnemonicDescriptionCPLGeneralPurposeBasic128-BitMedia64-BitMediax87SystemSUBSubtract3SUBPDSubtract Packed DoublePrecision Floating-Point3SSE2SUBPSSubtract Packed SinglePrecision Floating-Point3SSESUBSDSubtract Scalar DoublePrecision Floating-Point3SSE2SUBSSSubtract Scalar SinglePrecision Floating-Point3SSESWAPGSSwap GS Register withKernelGSbase MSR0Long ModeSYSCALLFast System Call3SYSCALL,SYSRETSYSENTERSystem Call3SYSENTER, SYSEXITSYSEXITSystem Return0SYSENTER, SYSEXITSYSRETFast System Return0SYSCALL,SYSRETTESTTest Bits3UCOMISDUnordered CompareScalar Double-PrecisionFloating-Point3SSE2UCOMISSUnordered CompareScalar Single-PrecisionFloating-Point3SSEUD2Undefined Operation3UNPCKHPDUnpack High DoublePrecision Floating-Point3SSE2UNPCKHPSUnpack High SinglePrecision Floating-Point3SSEUNPCKLPDUnpack Low DoublePrecision Floating-Point3SSE2UNPCKLPSUnpack Low SinglePrecision Floating-Point3SSEVERRVerify Segment for Reads3BasicVERWVerify Segment for Writes3BasicVMLOADLoad State from VMCB0SVMBasicBasicNote:1.
Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.432Instruction Subsets and CPUID Feature Sets24594—Rev.
3.13—July 2007Table D-1.AMD64 TechnologyInstruction Subsets and CPUID Feature Sets (continued)Instruction Subsetand CPUID Feature Set(s)1InstructionMnemonicVMMCALLDescriptionCPLGeneralPurpose128-BitMedia64-BitMediax87SystemCall VMM0SVMVMRUNRun Virtual Machine0SVMVMSAVESave State to VMCB0SVMWAITWait for x87 Floating-PointExceptions3WBINVDWriteback and InvalidateCaches0BasicWRMSRWrite to Model-SpecificRegister0RDMSR,WRMSRXADDExchange and Add3XCHGExchange3BasicXLATTranslate Table Index3BasicXLATBTranslate Table Index (NoOperands)3BasicXORExclusive OR3BasicXORPDLogical Bitwise ExclusiveOR Packed DoublePrecision Floating-Point3SSE2XORPSLogical Bitwise ExclusiveOR Packed SinglePrecision Floating-Point3SSEX87BasicNote:1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2.
Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Instruction Subsets and CPUID Feature Sets433AMD64 Technology43424594—Rev. 3.13—July 2007Instruction Subsets and CPUID Feature Sets24594—Rev. 3.13—July 2007AMD64 TechnologyAppendix E Instruction Effects on RFLAGSThe flags in the RFLAGS register are described in “Flags Register” in Volume 1 and “RFLAGSRegister” in Volume 2. Table E-1 summarizes the effect that instructions have on these flags. The tableincludes all instructions that affect the flags.
Instructions not shown have no effect on RFLAGS.The following codes are used within the table:••••0—The flag is always cleared to 0.1—The flag is always set to 1.AH—The flag is loaded with value from AH register.Mod—The flag is modified, depending on the results of the instruction.••••Pop—The flag is loaded with value popped off of the stack.Tst—The flag is tested.U—The effect on the flag is undefined.Gray shaded cells indicate that the flag is not affected by the instruction.Table E-1. Instruction Effects on RFLAGSInstructionMnemonicRFLAGS Mnemonic and Bit NumberID21VIP20VIF19AC18VM17RF16NT IOPL OF14 13-12 11DF10IF9TF8SF7ZF6AF4PF2CF0UUTstModUModUModUAAAAASUAADAAMUADCModMod Mod Mod ModADDModMod Mod Mod Mod ModAND0Mod ModMod ModARPLTstModUMod0ModBSFBSRUUModUUUBTBTCBTRBTSUUUUUModCLC0CLDCLI0ModTSTModCMCModCMOVccTstTstCMPModMod Mod Mod Mod ModCMPSxModInstruction Effects on RFLAGSTstTstTstTstMod Mod Mod Mod Mod435AMD64 Technology24594—Rev.
3.13—July 2007Table E-1. Instruction Effects on RFLAGS (continued)InstructionMnemonicRFLAGS Mnemonic and Bit NumberID21VIP20VIF19AC18VM17RF16NT IOPL OF14 13-12 11CMPXCHGDF10IF9TF8ModSF7ZF6ModCMPXCHG16BMod0DAADASUDECModDIVUPF2CF0Mod Mod Mod Mod ModCMPXCHG8BCOMISDCOMISSAF40ModMod Mod0Mod ModTstTstModModModMod Mod Mod ModUUUUUTstFCMOVccTstTstFCOMIFCOMIPFUCOMIFUCOMIPModMod ModIDIVUIMULModINCModINUUUUUUUUUModMod Mod Mod ModTstINSxTstTstINTINT 3TstMod ModMod0ModTstINTOModTstMod0ModTstTstIRETxPop Pop Pop PopTstTstPopPopPopTstPopPopMod0Mod ModPopPopPopTstJccPopPopTstTstLARPopTstTstTstLOOPELOOPNETstLSLModLZCNTUMOVSxUModUUModUUUUModTstMULModNEGModORMod Mod Mod Mod Mod0OUTTstOUTSxTstPOPCNT436PopModLODSxPOPFxPopMod ModTst Mod PopTst0PopTstPopMod0Tst0PopUPopPopPopPop0Mod000PopPopPopPopPopInstruction Effects on RFLAGS24594—Rev.
3.13—July 2007AMD64 TechnologyTable E-1. Instruction Effects on RFLAGS (continued)InstructionMnemonicRFLAGS Mnemonic and Bit NumberID21VIP20VIF19AC18VM17RF16NT IOPL OF14 13-12 11DF10IF9TF8SF7ZF6AF4PF2CF0RCL 1ModTstModRCL countUTstModRCR 1ModTstModRCR countUTstModROL 1ModModROL countUModROR 1ModModROR countUModRSMMod Mod Mod Mod Mod Mod Mod Mod Mod Mod Mod Mod Mod Mod Mod Mod ModSAHFAHAHAHAHAHSAL 1ModMod ModUMod ModSAL countUMod ModUMod ModSAR 1ModMod ModUMod ModSAR countUMod ModUMod ModSBBModSCASxModSETccTstTstSHLD 1SHRD 1ModMod ModUMod ModSHLD countSHRD countUMod ModUMod ModSHR 1ModMod ModUMod ModSHR countUMod ModUMod ModMod Mod Mod ModTstMod Mod Mod Mod ModTstTstSTC1ModTstModSTOSxTstSUBSYSCALLModMod Mod Mod ModSYSENTERSYSRETTst1STDSTITstModMod Mod Mod Mod000000Mod Mod Mod Mod Mod Mod Mod Mod Mod Mod ModTEST0UCOMISDUCOMISS0Instruction Effects on RFLAGSMod Mod Mod Mod ModMod Mod Mod Mod Mod Mod Mod Mod Mod Mod ModMod Mod0ModUMod00Mod Mod437AMD64 Technology24594—Rev.
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