Volume 3 General-Purpose and System Instructions (794097), страница 66
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No GPR register results.Promoted to64 bits.Operand sizeNo GPR register results.fixed at 64Stores 8-byte base and 2-byte limit.bits.SHL—Shift LeftD1 /4D3 /4Promoted to64 bits.32 bitsZero-extends 32bit registerUses 6-bit count.results to 64 bits.C1 /4Note:1. See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3.
If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits.
For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.394General-Purpose Instructions in 64-Bit Mode24594—Rev. 3.13—July 2007AMD64 TechnologyTable B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1Type ofOperation2DefaultOperandSize3Promoted to64 bits.32 bitsZero-extends 32bit registerUses 6-bit count.results to 64 bits.Promoted to64 bits.32 bitsZero-extends 32bit registerUses 6-bit count.results to 64 bits.Promoted to64 bits.32 bitsZero-extends 32bit registerUses 6-bit count.results to 64 bits.SHLD—Shift Left Double0F A40F A5For 32-BitOperand Size4For 64-BitOperand Size4SHR—Shift RightD1 /5D3 /5C1 /5SHRD—Shift Right Double0F AC0F ADSIDT—Store Interrupt Descriptor TableRegister0F 01 /1SKINIT—Secure Init and Jump withAttestation0F 01 DESLDT—Store Local Descriptor TableRegister0F 00 /0SMSW—Store Machine Status Word0F 01 /4STC—Set Carry FlagF9STD—Set Direction FlagFDPromoted to64 bits.Operand sizeNo GPR register results.fixed at 64Stores 8-byte base and 2-byte limit.bits.Same aslegacy mode.Zero-extends 32Not relevant bit registerresults to 64 bits.Same aslegacy mode.32Zero-extends 2-byte LDT selector to64 bits.Same aslegacy mode.32Zero-extends 32bit registerresults to 64 bits.Stores 64-bitmachine statusword (CR0).Same aslegacy mode.Not relevant.
No GPR register results.Same aslegacy mode.Not relevant. No GPR register results.Note:1. See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results.
See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5.
Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.General-Purpose Instructions in 64-Bit Mode395AMD64 Technology24594—Rev. 3.13—July 2007Table B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1STGI—Set Global Interrupt Flag0F 01 DCSTI - Set Interrupt FlagFBSTOS, STOSW, STOSD, STOSQ- StoreStringABSTR—Store Task Register0F 00 /1Type ofOperation2DefaultOperandSize3For 32-BitOperand Size4For 64-BitOperand Size4Not relevant.Same asNo GPR register results.legacy mode.Same aslegacy mode.Promoted to64 bits.Not relevant.
No GPR register results.32 bitsSTOSD: StoreStringDoublewords.See footnote5Same aslegacy mode.32Promoted to64 bits.32 bitsSTOSQ (newmnemonic):Store StringQuadwords.See footnote5Zero-extends 2-byte TR selector to64 bits.SUB—Subtract292B2DZero-extends 32bit registerresults to 64 bits.81 /583 /5SWAPGS—Swap GS Register withKernelGSbase MSR0F 01 /7SYSCALL—Fast System Call0F 05Newinstruction,available onlySee “SWAPGS Instruction” inin 64-bitNot relevant.Volume 2.mode. (Inother modes,this opcodeis invalid.)Promoted to64 bits.Not relevant.See “SYSCALL and SYSRETInstructions” in Volume 2 for details.Note:1. See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2.
The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4.
Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits.
For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.396General-Purpose Instructions in 64-Bit Mode24594—Rev. 3.13—July 2007AMD64 TechnologyTable B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1SYSENTER—System Call0F 34SYSEXIT—System Return0F 35SYSRET—Fast System Return0F 07Type ofOperation2DefaultOperandSize3For 32-BitOperand Size4For 64-BitOperand Size4INVALID IN LONG MODE (invalid-opcode exception)INVALID IN LONG MODE (invalid-opcode exception)Promoted to64 bits.32 bitsSee “SYSCALL and SYSRETInstructions” in Volume 2 for details.Promoted to64 bits.32 bitsNo GPR register results.TEST—Test Bits85A9F7 /0UD2—Undefined Operation0F 0BVERR—Verify Segment for Reads0F 00 /4VERW—Verify Segment for Writes0F 00 /5VMLOAD—Load State from VMCB0F 01 DAVMMCALL—Call VMM0F 01 D9VMRUN—Run Virtual Machine0F 01 D8VMSAVE—Save State to VMCB0F 01 DBSame aslegacy mode.Not relevant.
No GPR register results.Same aslegacy mode.Operand sizefixed at 16 No GPR register results.bitsSame aslegacy mode.Operand sizefixed at 16 No GPR register results.bitsSame aslegacy mode.Not relevant. No GPR register results.Same aslegacy mode.Not relevant. No GPR register results.Same aslegacy mode.Not relevant. No GPR register results.Same aslegacy mode.Not relevant. No GPR register results.Note:1. See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2.
The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4.
Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.General-Purpose Instructions in 64-Bit Mode397AMD64 Technology24594—Rev. 3.13—July 2007Table B-1.
Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1WAIT—Wait for Interrupt9BWBINVD—Writeback and Invalidate AllCaches0F 09WRMSR—Write to Model-SpecificRegister0F 30XADD—Exchange and Add0F C1XCHG—Exchange Register/Memorywith Register87Type ofOperation2DefaultOperandSize3For 32-BitOperand Size4For 64-BitOperand Size4Same aslegacy mode.Not relevant. No GPR register results.Same aslegacy mode.Not relevant.
No GPR register results.Same aslegacy mode.No GPR register results.Not relevant. MSR[63:32] = RDX[31:0]MSR[31:0] = RAX[31:0]Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.90XOR—Logical Exclusive OR31333581 /683 /6Note:1. See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3.
If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged.
Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.398General-Purpose Instructions in 64-Bit Mode24594—Rev.
3.13—July 2007B.3AMD64 TechnologyInvalid and Reassigned Instructions in 64-Bit ModeTable B-2 lists instructions that are illegal in 64-bit mode. Attempted use of these instructionsgenerates an invalid-opcode exception (#UD).Table B-2. Invalid Instructions in 64-Bit ModeMnemonicOpcode(hex)DescriptionAAA37ASCII Adjust After AdditionAADD5ASCII Adjust Before DivisionAAMD4ASCII Adjust After MultiplyAAS3FASCII Adjust After SubtractionBOUND62Check Array BoundsCALL (far)9AProcedure Call Far (far absolute)DAA27Decimal Adjust after AdditionDAS2FDecimal Adjust after SubtractionINTOCEInterrupt to Overflow VectorJMP (far)EAJump Far (absolute)LDSC5Load DS Far PointerLESC4Load ES Far PointerPOP DS1FPop Stack into DS SegmentPOP ES07Pop Stack into ES SegmentPOP SS17Pop Stack into SS SegmentPOPA, POPAD61Pop All to GPR Words or DoublewordsPUSH CS0EPush CS Segment Selector onto StackPUSH DS1EPush DS Segment Selector onto StackPUSH ES06Push ES Segment Selector onto StackPUSH SS16Push SS Segment Selector onto StackPUSHA,PUSHAD60Push All to GPR Words or DoublewordsRedundant Grp1SALC82 /2D6Redundant encoding of group1 Eb,IbopcodesSet AL According to CFGeneral-Purpose Instructions in 64-Bit Mode399AMD64 Technology24594—Rev.
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