Volume 3 General-Purpose and System Instructions (794097), страница 63
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See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged.
Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.General-Purpose Instructions in 64-Bit Mode381AMD64 Technology24594—Rev. 3.13—July 2007Table B-1.
Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1INVD—Invalidate Internal Caches0F 08INVLPG—Invalidate TLB Entry0F 01 /7INVLPGA—Invalidate TLB Entry in aSpecified ASIDType ofOperation2DefaultOperandSize3Jcc—Jump ConditionalPromoted to64 bits.Not relevant. No GPR register results.Same asNot relevant. No GPR register results.legacy mode.Promoted to64 bits.32 bitsIRETD: InterruptReturnDoubleword.See “Long-ModeInterrupt ControlTransfers” inVolume 2.Promoted to64 bits.64 bitsCan’t encode.60F 80 through 0F 8FE3IRETQ (newmnemonic):Interrupt ReturnQuadword.See “Long-ModeInterrupt ControlTransfers” inVolume 2.See “Near Branches in 64-Bit Mode” in Volume 1.70 through 7FJCXZ, JECXZ, JRCXZ—Jump onCX/ECX/RCX ZeroFor 64-BitOperand Size4Same asNot relevant.
No GPR register results.legacy mode.IRET, IRETD, IRETQ—Interrupt ReturnCFFor 32-BitOperand Size4Promoted to64 bits.64 bitsCan’t encode.6RIP = RIP + 8-bitdisplacementsign-extended to64 bits.RIP = RIP + 32bit displacementsign-extended to64 bits.RIP = RIP + 8-bitdisplacementsign-extended to64 bits.See footnote5Note:1. See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results.
See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4.
Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5.
Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.382General-Purpose Instructions in 64-Bit Mode24594—Rev. 3.13—July 2007AMD64 TechnologyTable B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1JMP—Jump NearType ofOperation2DefaultOperandSize3For 32-BitOperand Size4See “Near Branches in 64-Bit Mode” in Volume 1.RIP = RIP + 8-bitdisplacementsign-extended to64 bits.EBE9Promoted to64 bits.64 bitsCan’t encode.6EAFF /5LAHF - Load Status Flags into AHRegister9FLAR—Load Access Rights Byte0F 02LDS - Load DS Far PointerC5RIP = RIP + 32bit displacementsign-extended to64 bits.RIP = 64-bitoffset fromregister ormemory.FF /4JMP—Jump FarFor 64-BitOperand Size4See “Branches to 64-Bit Offsets” in Volume 1.INVALID IN 64-BIT MODE (invalid-opcode exception)Promoted to64 bits.32 bitsIf selector points to a gate, thenRIP = 64-bit offset from gate, elseRIP = zero-extended 32-bit offsetfrom far pointer referenced ininstruction.Same as legNot relevant.acy mode.Same aslegacy mode.32 bitsZero-extends 32bit registerresults to 64 bits.INVALID IN 64-BIT MODE (invalid-opcode exception)Note:1.
See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions.
Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits.
For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.General-Purpose Instructions in 64-Bit Mode383AMD64 Technology24594—Rev. 3.13—July 2007Table B-1. Operations and Operands in 64-Bit Mode (continued)Type ofOperation2DefaultOperandSize3For 32-BitOperand Size4Promoted to64 bits.32 bitsZero-extends 32bit registerresults to 64 bits.LEAVE—Delete Procedure Stack Frame Promoted to64 bits.C964 bitsCan’t encode6Instruction andOpcode (hex)1LEA—Load Effective Address8DLES - Load ES Far PointerC4LFENCE—Load Fence0F AE /5LFS—Load FS Far Pointer0F B4LGDT—Load Global Descriptor TableRegister0F 01 /2LGS—Load GS Far Pointer0F B5LIDT—Load Interrupt Descriptor TableRegister0F 01 /3LLDT—Load Local Descriptor TableRegister0F 00 /2LMSW—Load Machine Status Word0F 01 /6For 64-BitOperand Size4INVALID IN 64-BIT MODE (invalid-opcode exception)Same aslegacy mode.Same aslegacy mode.Promoted to64 bits.Same aslegacy mode.Not relevant.
No GPR register results.32 bitsZero-extends 32-bit register resultsto 64 bits.Operand size No GPR register results.fixed at 64Loads 8-byte base and 2-byte limit.bits.32 bitsZero-extends 32-bit register resultsto 64 bits.Promoted to64 bits.Operand sizeNo GPR register results.fixed at 64Loads 8-byte base and 2-byte limit.bits.Promoted to64 bits.Operand size No GPR register results.fixed at 16 References 16-byte descriptor tobits.load 64-bit base.Same aslegacy mode.Operand sizefixed at 16 No GPR register results.bits.Note:1.
See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3.
If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits.
For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.384General-Purpose Instructions in 64-Bit Mode24594—Rev. 3.13—July 2007AMD64 TechnologyTable B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1Type ofOperation2DefaultOperandSize3LODS, LODSW, LODSD, LODSQ—Load StringADPromoted to64 bits.32 bitsFor 32-BitOperand Size4For 64-BitOperand Size4LODSD: LoadStringDoublewords.Zero-extends 32bit registerresults to 64 bits.LODSQ (newmnemonic): LoadStringQuadwords.See footnoteSee footnote55LOOP—LoopE2LOOPZ, LOOPE—Loop if Zero/EqualE1Promoted to64 bits.64 bitsLOOPNZ, LOOPNE—Loop if NotZero/EqualCan’t encode.6RIP = RIP + 8-bitdisplacementsign-extended to64 bits.See footnote5E0LSL—Load Segment Limit0F 03LSS —Load SS Segment Register0F B2LTR—Load Task Register0F 00 /3Same aslegacy mode.32 bitsZero-extends 32-bit register resultsto 64 bits.Same aslegacy mode.32 bitsZero-extends 32-bit register resultsto 64 bits.Promoted to64 bits.LZCNT—Count Leading ZerosF3 0F BDPromoted to64 bits.MFENCE—Memory FenceSame aslegacy mode.0F AE /6MONITOR—Setup Monitor Address0F 01 C8Operand size No GPR register results.fixed at 16 References 16-byte descriptor tobits.load 64-bit base.32 bitsZero-extends 32-bit register resultsto 64 bits.Not relevant.
No GPR register results.Operand sizeSame asfixed at 32No GPR register results.legacy mode.bits.Note:1. See “General Rules for 64-Bit Mode” on page 373, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64Bit Mode” on page 373 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaultsto 64 bits. If the operand size is fixed, operand-size overrides are silently ignored.4.
Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, not source operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destination registers unchanged. Immediates and branch displacements are sign-extended to 64bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit addresssize, any pointer and count registers are zero-extended to 64 bits.6.
The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size overridein 64-bit mode.General-Purpose Instructions in 64-Bit Mode385AMD64 Technology24594—Rev. 3.13—July 2007Table B-1. Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex)1Type ofOperation2DefaultOperandSize3For 32-BitOperand Size4For 64-BitOperand Size4MOV—Move898BZero-extends 32bit register32-bit immediateresults to 64 bits.
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