Volume 3 General-Purpose and System Instructions (794097), страница 60
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In this table, Mnemonic Notation means theOpcode and Operand Encodings365AMD64 Technology24594—Rev. 3.13—July 2007syntax notation shown in “Mnemonic Syntax” on page 37 for a register, and ModRM Notation (/r)means the opcode-syntax notation shown in “Opcode Syntax” on page 39 for the register.Table A-15 on page 367 shows the encoding for 32-bit and 64-bit memory references using theModRM byte. This table describes 32-bit and 64-bit addressing, with the REX.B bit set or cleared.
TheEffective Address is shown in the two left-most columns, followed by the binary encoding of theModRM-byte mod field, followed by the eight possible hex values of the complete ModRM byte (onevalue for each binary encoding of the ModRM-byte reg field), followed by the binary encoding of theModRM r/m field.The /0 through /7 notation for the ModRM reg field (bits 5–3) means that the three-bit field contains avalue from zero (binary 000) to 7 (binary 111).Table A-14. ModRM Register References, 32-Bit and 64-Bit AddressingMnemonicNotationREX.R BitModRM reg Field/0/1/2/3/4/5/6/7reg8ALCLDLBLAH/SPLCH/BPLDH/SILBH/DILreg16AXCXDXBXSPBPSIDIreg32EAXECXEDXEBXESPEBPESIEDIreg64RAXRCXRDXRBXRSPRBPRSIRDIMMX0MMX1MMX2MMX3MMX4MMX5MMX6MMX7xmmXMM0XMM1XMM2XMM3XMM4XMM5XMM6XMM7sRegESCSSSDSFSGSinvalidinvalidcRegCR0CR1CR2CR3CR4CR5CR6CR7dRegDR0DR1DR2DR3DR4DR5DR6DR7reg8R8BR9BR10BR11BR12BR13BR14BR15Breg16R8WR9WR10WR11WR12WR13WR14WR15Wreg32R8DR9DR10DR11DR12DR13DR14DR15Dreg64R8R9R10R11R12R13R14R15MMX0MMX1MMX2MMX3MMX4MMX5MMX6MMX7xmmXMM8XMM9XMM10XMM11XMM12XMM13XMM14XMM15sRegESCSSSDSFSGSinvalidinvalidcRegCR8CR9CR10CR11CR12CR13CR14CR15dRegDR8DR9DR10DR11DR12DR13DR14DR15mmxmmx36601Opcode and Operand Encodings24594—Rev.
3.13—July 2007AMD64 TechnologyTable A-15. ModRM Memory References, 32-Bit and 64-Bit AddressingEffective Address1REX.B = 0REX.B = 1ModRMmodField(binary)ModRM reg Field3/0/1/2/3/4/5/6/7ModRMr/mField(binary)Complete ModRM Byte (hex)[rAX][r8]0008101820283038000[rCX][r9]0109111921293139001[rDX][r10]020A121A222A323A010[rBX][r11]030B131B232B333B011[SIB]4[SIB]4040C141C242C343C100[rIP+disp32] or [disp32]2[rIP+disp32] or[disp32]2050D151D252D353D101[rSI][r14]060E161E262E363E110[rDI][r15]070F171F272F373F111[rAX+disp8][r8+disp8]4048505860687078000[rCX+disp8][r9+disp8]4149515961697179001[rDX+disp8][r10+disp8]424A525A626A727A010[rBX+disp8][r11+disp8]434B535B636B737B011444C545C646C747C1000001[SIB+disp8]4[SIB+disp8]4[rBP+disp8][r13+disp8]454D555D656D757D101[rSI+disp8][r14+disp8]464E565E666E767E110[rDI+disp8][r15+disp8]474F575F676F777F111[rAX+disp32][r8+disp32]80889098A0A8B0B8000[rCX+disp32][r9+disp32]81899199A1A9B1B9001[rDX+disp32][r10+disp32]828A929AA2AAB2BA010[rBX+disp32][r11+disp32]838B939BA3ABB3BB011848C949CA4ACB4BC10010[SIB+disp32]4[SIB+disp32]4[rBP+disp32][r13+disp32]858D959DA5ADB5BD101[rSI+disp32][r14+disp32]868E969EA6AEB6BE110[rDI+disp32][r15+disp32]878F979FA7AFB7BF111Note:1.
In these combinations, “disp8” and “disp32” indicate an 8-bit or 32-bit signed displacement.2. In 64-bit mode, the effective address is [rIP+disp32]. In all other modes, the effective address is [disp32]. If theaddress-size prefix is used in 64-bit mode to override 64-bit addressing, the [RIP+disp32] effective address is truncated after computation to 64 bits.3.
See Table A-14 for complete specification of ModRM “reg” field.4. An SIB byte follows the ModRM byte to identify the memory operand.Opcode and Operand Encodings367AMD64 Technology24594—Rev. 3.13—July 2007Table A-15. ModRM Memory References, 32-Bit and 64-Bit Addressing (continued)Effective Address1REX.B = 0REX.B = 1ModRMmodField(binary)ModRM reg Field3/0/1/2/3/4/5/6/7ModRMr/mField(binary)Complete ModRM Byte (hex)AL/rAX/MMX0/XMM0r8/MMX0/XMM8C0C8D0D8E0E8F0F8000CL/rCX/MMX1/XMM1r9/MMX1/XMM9C1C9D1D9E1E9F1F9001DL/rDX/MMX2/XMM2r10/MMX2/XMM10C2CAD2DAE2EAF2FA010BL/rBX/MMX3/XMM3r11/MMX3/XMM11C3CBD3DBE3EBF3FB011C4CCD4DCE4ECF4FC100CH/BPL/rBP/MMX5/XM r13/MMX5/XMM1M53C5CDD5DDE5EDF5FD101DH/SIL/rSI/MMX6/XMM r14/MMX6/XMM164C6CED6DEE6EEF6FE110BH/DIL/rDI/MMX7/XMM r15/MMX7/XMM175C7CFD7DFE7EFF7FF111AH/SPL/rSP/MMX4/XM r12/MMX4/XMM1M4211Note:1.
In these combinations, “disp8” and “disp32” indicate an 8-bit or 32-bit signed displacement.2. In 64-bit mode, the effective address is [rIP+disp32]. In all other modes, the effective address is [disp32]. If theaddress-size prefix is used in 64-bit mode to override 64-bit addressing, the [RIP+disp32] effective address is truncated after computation to 64 bits.3. See Table A-14 for complete specification of ModRM “reg” field.4.
An SIB byte follows the ModRM byte to identify the memory operand.A.3.2 SIB Operand ReferencesFigure A-3 on page 369 shows the format of a scale-index-base (SIB) byte. Some instructions have anSIB byte following their ModRM byte to define memory addressing for the complex-addressingmodes described in “Effective Addresses” in Volume 1. The SIB byte has three fields—scale, index,and base—that define the scale factor, index-register number, and base-register number for 32-bit and64-bit complex addressing modes. In 64-bit mode, the REX.B and REX.X bits extend the encoding ofthe SIB byte’s base and index fields.368Opcode and Operand Encodings24594—Rev. 3.13—July 2007Bits:AMD64 Technology7654scale3index210SIBbaseREX.X bit of REX prefix canextend this field to 4 bits513-306.epsREX.B bit of REX prefix canextend this field to 4 bitsFigure A-3.SIB Byte FormatTable A-16 shows the encodings for the SIB byte’s base field, which specifies the base register foraddressing.
Table A-17 on page 370 shows the encodings for the effective address referenced by acomplete SIB byte, including its scale and index fields. The /0 through /7 notation for the SIB basefield means that the three-bit field contains a value between zero (binary 000) and 7 (binary 111).Table A-16. SIB base Field ReferencesREX.B BitModRM mod FieldSIB base Field/0/1/2/3/4000101/5rAXrCXrDXrBXrSPrBP+disp8rBP+disp3200disp3210Opcode and Operand Encodings/7rSIrDIr14r15disp321001/6r8r9r10r11r12r13+disp8r13+disp32369AMD64 Technology24594—Rev. 3.13—July 2007Table A-17. SIB Memory ReferencesSIB base Field1REX.B = 0: rAX rCX rDX rBX rSPEffective AddressREX.X = 0SIBSIBscale indexField Field REX.B = 1:r8r9r10r11r12/0/1/2/3/4REX.X = 1noterSIrDI1r14r15/5/6/71noteComplete SIB Byte (hex)[rAX+base][r8+base]0000001020304050607[rCX+base][r9+base]00108090A0B0C0D0E0F[rDX+base][r10+base]0101011121314151617[rBX+base][r11+base]01118191A1B1C1D1E1F00[base][r12+base]1002021222324252627[rBP+base][r13+base]10128292A2B2C2D2E2F[rSI+base][r14+base]1103031323334353637[rDI+base][r15+base]11138393A3B3C3D3E3F[rAX*2+base][r8*2+base]0004041424344454647[rCX*2+base][r9*2+base]00148494A4B4C4D4E4F[rDX*2+base][r10*2+base]0105051525354555657[rBX*2+base][r11*2+base]01158595A5B5C5D5E5F01[base][r12*2+base]1006061626364656667[rBP*2+base][r13*2+base]10168696A6B6C6D6E6F[rSI*2+base][r14*2+base]1107071727374757677[rDI*2+base][r15*2+base]11178797A7B7C7D7E7F[rAX*4+base][r8*4+base]0008081828384858687[rCX*4+base][r9*4+base]00188898A8B8C8D8E8F[rDX*4+base][r10*4+base]0109091929394959697[rBX*4+base][r11*4+base]01198999A9B9C9D9E9F10[base][r12*4+base]100A0A1A2A3A4A5A6A7[rBP*4+base][r13*4+base]101A8A9AAABACADAEAF[rSI*4+base][r14*4+base]110B0B1B2B3B4B5B6B7[rDI*4+base][r15*4+base]111B8B9BABBBCBDBEBFNote:1.
See Table A-16 on page 369 for complete specification of SIB “base” field.370Opcode and Operand Encodings24594—Rev. 3.13—July 2007AMD64 TechnologyTable A-17. SIB Memory References (continued)SIB base Field1REX.B = 0: rAX rCX rDX rBX rSPEffective AddressREX.X = 0SIBSIBscale indexField Field REX.B = 1:r8r9r10r11r12/0/1/2/3/4REX.X = 1noterSIrDI1r14r15/5/6/71noteComplete SIB Byte (hex)[rAX*8+base][r8*8+base]000C0C1C2C3C4C5C6C7[rCX*8+base][r9*8+base]001C8C9CACBCCCDCECF[rDX*8+base][r10*8+base]010D0D1D2D3D4D5D6D7[rBX*8+base][r11*8+base]011D8D9DADBDCDDDEDF11[base][r12*8+base]100E0E1E2E3E4E5E6E7[rBP*8+base][r13*8+base]101E8E9EAEBECEDEEEF[rSI*8+base][r14*8+base]110F0F1F2F3F4F5F6F7[rDI*8+base][r15*8+base]111F8F9FAFBFCFDFEFFNote:1. See Table A-16 on page 369 for complete specification of SIB “base” field.Opcode and Operand Encodings371AMD64 Technology37224594—Rev.
3.13—July 2007Opcode and Operand Encodings24594—Rev. 3.13—July 2007AMD64 TechnologyAppendix B General-Purpose Instructions in64-Bit ModeThis appendix provides details of the general-purpose instructions in 64-bit mode and its differencesfrom legacy and compatibility modes. The appendix covers only the general-purpose instructions(those described in Chapter 3, “General-Purpose Instruction Reference”). It does not cover the 128bit media, 64-bit media, or x87 floating-point instructions because those instructions are not affectedby 64-bit mode, other than in the access by such instructions to extended GPR and XMM registerswhen using a REX prefix.B.1General Rules for 64-Bit ModeIn 64-bit mode, the following general rules apply to instructions and their operands:••••••••“Promoted to 64 Bit”: If an instruction’s operand size (16-bit or 32-bit) in legacy andcompatibility modes depends on the CS.D bit and the operand-size override prefix, then theoperand-size choices in 64-bit mode are extended from 16-bit and 32-bit to include 64 bits (with aREX prefix), or the operand size is fixed at 64 bits.
Such instructions are said to be “Promoted to64 bits” in Table B-1. However, byte-operand opcodes of such instructions are not promoted.Byte-Operand Opcodes Not Promoted: As stated above in “Promoted to 64 Bit”, byte-operandopcodes of promoted instructions are not promoted. Those opcodes continue to operate only onbytes.Fixed Operand Size: If an instruction’s operand size is fixed in legacy mode (thus, independent ofCS.D and prefix overrides), that operand size is usually fixed at the same size in 64-bit mode. Forexample, CPUID operates on 32-bit operands, irrespective of attempts to override the operand size.Default Operand Size: The default operand size for most instructions is 32 bits, and a REX prefixmust be used to change the operand size to 64 bits.
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