Volume 3 General-Purpose and System Instructions (794097), страница 55
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3.13—July 2007BR_TOLASTEXCP_FROMLASTEXCP_TOif (guest state consistency checks fail)#VMEXIT(INVALID)Execute command stored in TLB_CONTROL.GIF = 1// allow interrupts in the guestif (EVENTINJ.V)cause exception/interrupt in guestelsejump to first guest instructionUpon #VMEXIT, the processor performs the following actions in order to return to the host executioncontext:GIF = 0save guest state to VMCB:ES.{base,limit,attr,sel}CS.{base,limit,attr,sel}SS.{base,limit,attr,sel}DS.{base,limit,attr,sel}GDTR.{base,limit}IDTR.{base,limit}EFERCR4CR3CR2CR0if (nested paging enabled)gPATRFLAGSRIPRSPRAXDR7DR6CPLINTERRUPT_SHADOWsave additional state and intercept information:V_IRQ, V_TPREXITCODEEXITINFO1EXITINFO2EXITINTINFOclear EVENTINJ field in VMCBprepare for host mode by clearing internal processor state bits:clear interceptsclear v_irq332VMRUNInstruction Reference24594—Rev.
3.13—July 2007AMD64 Technologyclear v_intr_maskingclear tsc_offsetdisable nested pagingclear ASID to zeroreload host stateGDTR.{base,limit}IDTR.{base,limit}EFERCR0CR0.PE = 1 // saved copy of CR0.PE isCR4CR3if (host is in PAE paging mode)reloaded host PDPEs// Do not reload host CR2 or PATRFLAGSRIPRSPRAXDR7 = “all disabled”CPL = 0ES.sel; reload segment descriptor fromCS.sel; reload segment descriptor fromSS.sel; reload segment descriptor fromDS.sel; reload segment descriptor fromignoredGDTGDTGDTGDTif (LBR virtualization supported)LBR_VIRTUALIZATION_ENABLEif (LBR_VIRTUALIZATION_ENABLE=1)save LBR state to the VMCB:DBGCTLBR_FROMBR_TOLASTEXCP_FROMLASTEXCP_TOload LBR state from the host save area:DBGCTLBR_FROMBR_TOLASTEXCP_FROMLASTEXCP_TOif (illegal host state loaded, or exception while loading host state)shutdownelseexecute first host instruction following the VMRUNRelated InstructionsVMLOAD, VMSAVE.Instruction ReferenceVMRUN333AMD64 Technology24594—Rev.
3.13—July 2007rFLAGS AffectedNone.ExceptionsExceptionVirtualReal 8086 ProtectedXXInvalid opcode, #UDXGeneral protection,#GP334Cause of ExceptionXThe SVM instructions are not supported as indicated by ECXbit 2 as returned by CPUID function 8000_0001h.XSecure Virtual Machine was not enabled (EFER.SVME=0).XThe instruction is only recognized in protected mode.XCPL was not zero.XrAX referenced a physical address above the maximumsupported physical address.XThe address in rAX was not aligned on a 4Kbyte boundary.VMRUNInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyVMSAVESave State to VMCBStores a subset of the processor state into the VMCB specified by the physical address in the rAXregister (the portion of RAX used to form the address is determined by the effective address size).The VMSAVE and VMLOAD instructions complement the state save/restore abilities of VMRUN and#VMEXIT, providing access to hidden state that software is otherwise unable to access, plus someadditional commonly-used state.This is a Secure Virtual Machine instruction. This instruction generates a #UD exception if SVM isnot enabled. See “Enabling SVM” on page 367 in AMD64 Architecture Programmer’s ManualVolume 2: System Instructions, order# 24593.MnemonicVMSAVE rAXOpcode0F 01 DBDescriptionSave additional guest state to VMCB.ActionIF ((MSR_EFER.SVME = 0) || (!PROTECTED_MODE))EXCEPTION [#UD]// This instruction can only be executed in protected// mode with SVM enabledIF (CPL != 0)EXCEPTION [#GP]// This instruction is only allowed at CPL 0IF (rAX contains an unsupported physical address)EXCEPTION [#GP]Store to a VMCB at physical address rAX:FS, GS, TR, LDTR (including all hidden state)KernelGsBaseSTAR, LSTAR, CSTAR, SFMASKSYSENTER_CS, SYSENTER_ESP, SYSENTER_EIPRelated InstructionsVMLOADrFLAGS AffectedNone.System Instruction Reference335AMD64 Technology24594—Rev.
3.13—July 2007ExceptionsExceptionVirtualReal 8086 ProtectedXXInvalid opcode, #UDXGeneral protection,#GP336Cause of ExceptionXThe SVM instructions are not supported as indicated by ECXbit 2 as returned by CPUID function 8000_0001h.XSecure Virtual Machine was not enabled (EFER.SVME=0).XThe instruction is only recognized in protected mode.XCPL was not zero.XrAX referenced a physical address above the maximumsupported physical address.XThe address in rAX was not aligned on a 4Kbyte boundary.System Instruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyWBINVDWriteback and Invalidate CachesWrites all modified cache lines in the internal caches back to main memory and invalidates (flushes)internal caches. It then causes external caches to write back modified data to main memory; theexternal caches are subsequently invalidated. After invalidating internal caches, the processorproceeds immediately with the execution of the next instruction without waiting for external hardwareto invalidate its caches.The INVD instruction can be used when cache coherence with memory is not important.This instruction does not invalidate TLB caches.This is a privileged instruction.
The current privilege level of a procedure invalidating the processor’sinternal caches must be zero.WBINVD is a serializing instruction.MnemonicOpcodeWBINVD0F 09DescriptionWrite modified cache lines to main memory, invalidateinternal caches, and trigger external cache flushes.Related InstructionsCLFLUSH, INVDrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedGeneral protection,#GPSystem Instruction ReferenceXXCause of ExceptionCPL was not 0.337AMD64 Technology24594—Rev.
3.13—July 2007WRMSRWrite to Model-Specific RegisterWrites data to 64-bit model-specific registers (MSRs). These registers are widely used in performancemonitoring and debugging applications, as well as testability and program execution tracing.This instruction writes the contents of the EDX:EAX register pair into a 64-bit model-specific registerspecified in the ECX register.
The 32 bits in the EDX register are mapped into the high-order bits of themodel-specific register and the 32 bits in EAX form the low-order 32 bits.This instruction must be executed at a privilege level of 0 or a general protection fault #GP(0) will beraised. This exception is also generated if an attempt is made to specify a reserved or unimplementedmodel-specific register in ECX.WRMSR is a serializing instruction.The CPUID instruction can provide model information useful in determining the existence of aparticular MSR.See Volume 2: System Programming, for more information about model-specific registers, machinecheck architecture, performance monitoring and debug registers.MnemonicOpcodeWRMSR0F 30DescriptionWrite EDX:EAX to the MSR specified by ECX.Related InstructionsRDMSRrFLAGS AffectedNoneExceptionsExceptionInvalid opcode, #UDGeneral protection,#GP338VirtualReal 8086 ProtectedCause of ExceptionXXThe WRMSR instruction is not supported, as indicated byEDX bit 5 returned by CPUID function 1 or 8000_0001h.XXCPL was not 0.XXThe value in ECX specifies a reserved or unimplementedMSR address.XXWriting 1 to any bit that must be zero (MBZ) in the MSR.XXWriting a non-canonical value to a MSR that can only bewritten with canonical values.XSystem Instruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyAppendix A Opcode and Operand EncodingsThis section specifies the hexadecimal and/or binary encodings for the opcodes and the implicitoperand references used in the AMD64 instruction set. For an overview of the instruction formats towhich these encodings apply, see Chapter 1, “Instruction Formats.”A.1Opcode-Syntax NotationThe following notation is used in this section to specify opcodes and their operands:AFar pointer is encoded in the instruction.CControl register specified by the ModRM reg field.DDebug register specified by the ModRM reg field.EGeneral purpose register or memory operand specified by the ModRM byte.
Memory addressescan be computed from a segment register, SIB byte, and/or displacement.FrFLAGS register.GGeneral purpose register specified by the ModRM reg field.IImmediate value.JThe instruction includes a relative offset that is added to the rIP.MA memory operand specified by the ModRM byte.OThe offset of an operand is encoded in the instruction. There is no ModRM byte in theinstruction. Complex addressing using the SIB byte cannot be done.P64-bit MMX register specified by the ModRM reg field.PR64-bit MMX register specified by the ModRM r/m field. The ModRM mod field must be 11b.Q64-bit MMX-register or memory operand specified by the ModRM byte.
Memory addresses canbe computed from a segment register, SIB byte, and/or displacement.RGeneral purpose register specified by the ModRM r/m field. The ModRM mod field must be 11b.SSegment register specified by the ModRM reg field.V128-bit XMM register specified by the ModRM reg field.VR128-bit XMM register specified by the ModRM r/m field. The ModRM mod field must be 11b.WA 128-bit XMM register or memory operand specified by the ModRM byte. Memory addressescan be computed from a segment register, SIB byte, and/or displacement.XA memory operand addressed by the DS.rSI registers. Used in string instructions.YA memory operand addressed by the ES.rDI registers. Used in string instructions.Opcode and Operand Encodings339AMD64 Technology24594—Rev.
3.13—July 2007aTwo 16-bit or 32-bit memory operands, depending on the effective operand size. Used in theBOUND instruction.bA byte, irrespective of the effective operand size.dA doubleword (32 bits), irrespective of the effective operand size.dqA double-quadword (128 bits), irrespective of the effective operand size.pA 32-bit or 48-bit far pointer, depending on the effective operand size.pdA 128-bit double-precision floating-point vector operand (packed double).piA 64-bit MMX operand (packed integer).psA 128-bit single-precision floating-point vector operand (packed single).qA quadword, irrespective of the effective operand size.sA 6-byte or 10-byte pseudo-descriptor.sdA scalar double-precision floating-point operand (scalar double).siA scalar doubleword (32-bit) integer operand (scalar integer).ssA scalar single-precision floating-point operand (scalar single).vA word, doubleword, or quadword, depending on the effective operand size.wA word, irrespective of the effective operand size.zA word if the effective operand size is 16 bits, or a doubleword if the effective operand size is 32or 64 bits./nA ModRM-byte reg field or SIB-byte base field that contains a value (n) between zero (binary000) and 7 (binary 111).For definitions of the mnemonics used to name registers, see “Summary of Registers and Data Types”on page 24.A.2Opcode EncodingsA.2.1 One-Byte OpcodesTable A-1 on page 341 shows the one-byte opcodes in which the low nibble is in the range 0–7h.Table A-2 on page 342 shows those opcodes in which the low nibble is in the range 8–Fh.
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