Volume 3 General-Purpose and System Instructions (794097), страница 54
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A flag set to one or cleared to zero is M (modified). Unaffected flagsare blank. Undefined flags are U.ExceptionsExceptionRealVirtual8086ProtectedXXXThe SYSCALL and SYSRET instructions are notsupported, as indicated by EDX bit 11 returned byCPUID function 8000_0001h.XXXThe system call extension bit (SCE) of the extendedfeature enable register (EFER) is set to 0. (TheEFER register is MSR C000_0080h.)XXInvalid opcode, #UDGeneral protection, #GPThis instruction is only recognized in protectedmode.X322Cause of ExceptionCPL was not 0.SYSRETInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologyUD2Undefined OperationGenerates an invalid opcode exception.
Unlike other undefined opcodes that may be defined as legalinstructions in the future, UD2 is guaranteed to stay undefined.MnemonicOpcodeUD2Description0F 0BRaise an invalid opcode exception.Related InstructionsNonerFLAGS AffectedNoneExceptionsExceptionInvalid opcode, #UDVirtualReal 8086 ProtectedXInstruction ReferenceXXCause of ExceptionThis instruction is not recognized.UD2323AMD64 Technology24594—Rev. 3.13—July 2007VERRVerify Segment for ReadsVerifies whether a code or data segment specified by the segment selector in the 16-bit register ormemory operand is readable from the current privilege level. The zero flag (ZF) is set to 1 if thespecified segment is readable.
Otherwise, ZF is cleared.A segment is readable if all of the following apply:••••the selector is not a null selector.the descriptor is within the GDT or LDT limit.the segment is a data segment or readable code segment.the descriptor DPL is greater than or equal to both the CPL and RPL, or the segment is a conforming code segment.The processor does not recognize the VERR instruction in real or virtual-8086 mode.MnemonicOpcodeVERR reg/mem16DescriptionSet the zero flag (ZF) to 1 if the segmentselected can be read.0F 00 /4Related InstructionsARPL, LAR, LSL, VERWrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCF420M2120191817161413–1211109876Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to one or cleared to zero is M (modified). Unaffected flagsare blank. Undefined flags are U.ExceptionsExceptionInvalid opcode, #UDVirtualReal 8086 ProtectedXXCause of ExceptionThis instruction is only recognized in protected mode.Stack, #SSXA memory address exceeded the stack segment limit or isnon-canonical.General protection,#GPXA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to reference memory.324VERRInstruction Reference24594—Rev.
3.13—July 2007ExceptionAMD64 TechnologyVirtualReal 8086 ProtectedCause of ExceptionPage fault, #PFXA page fault resulted from the execution of the instruction.Alignment check,#ACXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceVERR325AMD64 Technology24594—Rev. 3.13—July 2007VERWVerify Segment for WriteVerifies whether a data segment specified by the segment selector in the 16-bit register or memoryoperand is writable from the current privilege level. The zero flag (ZF) is set to 1 if the specifiedsegment is writable. Otherwise, ZF is cleared.A segment is writable if all of the following apply:••••the selector is not a null selector.the descriptor is within the GDT or LDT limit.the segment is a writable data segment.the descriptor DPL is greater than or equal to both the CPL and RPL.The processor does not recognize the VERW instruction in real or virtual-8086 mode.MnemonicOpcodeVERW reg/mem16DescriptionSet the zero flag (ZF) to 1 if the segmentselected can be written.0F 00 /5Related InstructionsARPL, LAR, LSL, VERRrFLAGS AffectedIDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCF420M2120191817161413–1211109876Note: Bits 31–22, 15, 5, 3, and 1 are reserved.
A flag set to one or cleared to zero is M (modified). Unaffected flagsare blank. Undefined flags are U.ExceptionsExceptionInvalid opcode, #UDVirtualReal 8086 ProtectedXXCause of ExceptionThis instruction is only recognized in protected mode.Stack, #SSXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXA memory address exceeded a data segment limit or was noncanonical.XA null data segment was used to access memory.Page fault, #PFXA page fault resulted from the execution of the instruction.Alignment check,#ACXAn unaligned memory reference was performed whilealignment checking was enabled.326VERWInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyVMLOADLoad State from VMCBLoads a subset of processor state from the VMCB specified by the physical address in the rAX register.The portion of RAX used to form the address is determined by the effective address size.The VMSAVE and VMLOAD instructions complement the state save/restore abilities of VMRUN and#VMEXIT, providing access to hidden state that software is otherwise unable to access, plus someadditional commonly-used state.This is a Secure Virtual Machine instruction. This instruction generates a #UD exception if SVM isnot enabled.
See “Enabling SVM” on page 367 in AMD64 Architecture Programmer’s ManualVolume 2: System Instructions, order# 24593.MnemonicVMLOAD rAXOpcodeDescription0F 01 DALoad additional state from VMCB.ActionIF ((MSR_EFER.SVME = 0) || (!PROTECTED_MODE))EXCEPTION [#UD]// This instruction can only be executed in protected// mode with SVM enabledIF (CPL != 0)EXCEPTION [#GP]//This instruction is only allowed at CPL 0IF (rAX contains an unsupported physical address)EXCEPTION [#GP]Load from a VMCB at physical address rAX:FS, GS, TR, LDTR (including all hidden state)KernelGsBaseSTAR, LSTAR, CSTAR, SFMASKSYSENTER_CS, SYSENTER_ESP, SYSENTER_EIPRelated InstructionsVMSAVErFLAGS AffectedNone.Instruction ReferenceVMLOAD327AMD64 Technology24594—Rev. 3.13—July 2007ExceptionsExceptionVirtualReal 8086 ProtectedXXInvalid opcode, #UDXGeneral protection,#GP328Cause of ExceptionXThe SVM instructions are not supported as indicated by ECXbit 2 as returned by CPUID function 8000_0001h.XSecure Virtual Machine was not enabled (EFER.SVME=0).XThe instruction is only recognized in protected mode.XCPL was not zero.XrAX referenced a physical address above the maximumsupported physical address.XThe address in rAX was not aligned on a 4Kbyte boundary.VMLOADInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyVMMCALLCall VMMProvides a mechanism for a guest to explicitly communicate with the VMM by generating a#VMEXIT.A non-intercepted VMMCALL unconditionally raises a #UD exception.VMMCALL is not restricted to either protected mode or CPL zero.This is a Secure Virtual Machine instruction.
This instruction generates a #UD exception if SVM isnot enabled. See “Enabling SVM” on page 367 in AMD64 Architecture Programmer’s ManualVolume 2: System Instructions, order# 24593.MnemonicOpcodeVMMCALLDescription0F 01 D9Explicit communication with the VMM.Related InstructionsNone.rFLAGS AffectedNone.ExceptionsExceptionVirtualReal 8086 ProtectedInvalid opcode, #UDInstruction ReferenceCause of ExceptionXXXThe SVM instructions are not supported as indicated by ECXbit 2 as returned by CPUID function 8000_0001h.XXXSecure Virtual Machine was not enabled (EFER.SVME=0).XXXVMMCALL was not intercepted.VMMCALL329AMD64 Technology24594—Rev. 3.13—July 2007VMRUNRun Virtual MachineStarts execution of a guest instruction stream.
The physical address of the virtual machine controlblock (VMCB) describing the guest is taken from the rAX register (the portion of RAX used to formthe address is determined by the effective address size).VMRUN saves a subset of host processor state to the host state-save area specified by the physicaladdress in the VM_HSAVE_PA MSR. VMRUN then loads guest processor state (and controlinformation) from the VMCB at the physical address specified in rAX. The processor then executesguest instructions until one of several intercept events (specified in the VMCB) is triggered. When anintercept event occurs, the processor stores a snapshot of the guest state back into the VMCB, reloadsthe host state, and continues execution of host code at the instruction following the VMRUNinstruction.This is a Secure Virtual Machine instruction.
This instruction generates a #UD exception if SVM isnot enabled. See “Enabling SVM” on page 367 in AMD64 Architecture Programmer’s ManualVolume 2: System Instructions, order# 24593.MnemonicVMRUN rAXOpcode0F 01 D8DescriptionPerforms a world-switch to guest.ActionIF ((MSR_EFER.SVME = 0) || (!PROTECTED_MODE))EXCEPTION [#UD]// This instruction can only be executed in protected// mode with SVM enabledIF (CPL != 0)EXCEPTION [#GP]//This instruction is only allowed at CPL 0IF (rAX contains an unsupported physical address)EXCEPTION [#GP]if (intercepted(VMRUN))#VMEXIT (VMRUN)remember VMCB address (delivered in rAX) for next #VMEXITsave host state to physical memory indicated in the VM_HSAVE_PA MSR:ES.selCS.selSS.selDS.selGDTR.{base,limit}IDTR.{base,limit}EFERCR0CR4CR3// host CR2 is not savedRFLAGS330VMRUNInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyRIPRSPRAXfrom the VMCB at physical address rAX, load control information:intercept vectorTSC_OFFSETinterrupt control (v_irq, v_intr_*, v_tpr)EVENTINJ fieldASIDif (nested paging supported)NP_ENABLEif (NP_ENABLE = 1)nCR3from the VMCB at physical address rAX, load guest state:ES.{base,limit,attr,sel}CS.{base,limit,attr,sel}SS.{base,limit,attr,sel}DS.{base,limit,attr,sel}GDTR.{base,limit}IDTR.{base,limit}EFERCR0CR4CR3CR2if (NP_ENABLE = 1)gPAT// Leaves host hPAT register unchanged.RFLAGSRIPRSPRAXDR7DR6CPL// 0 for real mode, 3 for v86 mode, else as loaded.INTERRUPT_SHADOWif (LBR virtualization supported)LBR_VIRTUALIZATION_ENABLEif (LBR_VIRTUALIZATION_ENABLE=1)save LBR state to the host save areaDBGCTLBR_FROMBR_TOLASTEXCP_FROMLASTEXCP_TOload LBR state from the VMCBDBGCTLBR_FROMInstruction ReferenceVMRUN331AMD64 Technology24594—Rev.
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