Volume 3 General-Purpose and System Instructions (794097), страница 50
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3.13—July 2007RDTSCRead Time-Stamp CounterLoads the value of the processor’s 64-bit time-stamp counter into registers EDX:EAX.The time-stamp counter (TSC) is contained in a 64-bit model-specific register (MSR). The processorsets the counter to 0 upon reset and increments the counter every clock cycle. INIT does not modify theTSC.The high-order 32 bits are loaded into EDX, and the low-order 32 bits are loaded into the EAX register.This instruction ignores operand size.When the time-stamp disable flag (TSD) in CR4 is set to 1, the RDTSC instruction can only be used atprivilege level 0. If the TSD flag is 0, this instruction can be used at any privilege level.This instruction is not serializing. Therefore, there is no guarantee that all instructions have completedat the time the time-stamp counter is read.The behavior of the RDTSC instruction is implementation dependent.
The TSC counts at a constantrate, but may be affected by power management events (such as frequency changes), depending on theprocessor implementation. If CPUID 8000_0007.edx[8] = 1, then the TSC rate is ensured to beinvariant across all P-States, C-States, and stop-grant transitions (such as STPCLK Throttling);therefore, the TSC is suitable for use as a source of time. Consult the BIOS and kernel developer’sguide for your AMD processor implementation for information concerning the effect of powermanagement on the TSC.MnemonicOpcodeRDTSC0F 31DescriptionCopy the time-stamp counter into EDX:EAX.Related InstructionsRDTSCP, RDMSR, WRMSRrFLAGS AffectedNoneExceptionsExceptionInvalid opcode, #UDGeneral protection,#GP294VirtualReal 8086 ProtectedXCause of ExceptionXXThe RDTSC instruction is not supported, as indicated byEDX bit 4 returned by CPUID function 0000_0001h orfunction 8000_0001h.XXCPL was not 0 and CR4.TSD = 1.RDTSCInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologyRDTSCPRead Time-Stamp Counterand Processor IDLoads the value of the processor’s 64-bit time-stamp counter into registers EDX:EAX, and loads thevalue of TSC_AUX into ECX. This instruction ignores operand size.The time-stamp counter is contained in a 64-bit model-specific register (MSR).
The processor sets thecounter to 0 upon reset and increments the counter every clock cycle. INIT does not modify the TSC.The high-order 32 bits are loaded into EDX, and the low-order 32 bits are loaded into the EAX register.The TSC_AUX value is contained in the low-order 32 bits of the TSC_AUX register (MSR addressC000_0103h). This MSR is initialized by privileged software to any meaningful value, such as aprocessor ID, that software wants to associate with the returned TSC value.When the time-stamp disable flag (TSD) in CR4 is set to 1, the RDTSCP instruction can only be usedat privilege level 0.
If the TSD flag is 0, this instruction can be used at any privilege level.Unlike the RDTSC instruction, RDTSCP forces all younger instructions to retire before reading thetime-stamp counter.The behavior of the RDTSCP instruction is implementation dependent. The TSC counts at a constantrate, but may be affected by power management events (such as frequency changes), depending on theprocessor implementation. If CPUID 8000_0007.edx[8] = 1, then the TSC rate is ensured to beinvariant across all P-States, C-States, and stop-grant transitions (such as STPCLK Throttling);therefore, the TSC is suitable for use as a source of time. Consult the BIOS and kernel developer’sguide for your AMD processor implementation for information concerning the effect of powermanagement on the TSC.Use the CPUID instruction to verify support for this instruction.MnemonicRDTSCPOpcode0F 01 F9DescriptionCopy the time-stamp counter into EDX:EAX andthe TSC_AUX register into ECX.Related InstructionsRDTSCrFLAGS AffectedNoneInstruction ReferenceRDTSCP295AMD64 Technology24594—Rev.
3.13—July 2007ExceptionsExceptionInvalid opcode, #UDGeneral protection,#GP296VirtualReal 8086 ProtectedXCause of ExceptionXXThe RDTSCP instruction is not supported, as indicated byEDX bit 27 returned by CPUID function 8000_0001h.XXCPL was not 0 and CR4.TSD = 1.RDTSCPInstruction Reference24594—Rev. 3.13—July 2007RSMAMD64 TechnologyResume from System Management ModeResumes an operating system or application procedure previously interrupted by a systemmanagement interrupt (SMI). The processor state is restored from the information saved when the SMIwas taken.
If the processor detects invalid state information in the system management mode (SMM)save area during RSM, it goes into a shutdown state.RSM will shutdown if any of the following conditions are found in the save map (SSM):•••••An illegal combination of flags in CR0 (CR0.PG = 1 and CR0.PE = 0, or CR0.NW = 1 andCR0.CD = 0).A reserved bit in CR0, CR3, CR4, DR6, DR7, or the extended feature enable register (EFER) isset to 1.The following bit combination occurs: EFER.LME = 1, CR0.PG = 1, CR4.PAE = 0.The following bit combination occurs: EFER.LME = 1, CR0.PG = 1, CR4.PAE = 1, CS.D = 1,CS.L = 1.SMM revision field has been modified.RSM cannot modify EFER.SVME.
Attempts to do so are ignored.When EFER.SVME is 1, RSM reloads the four PDPEs (through the incoming CR3) when returning toa mode that has legacy PAE mode paging enabled.When EFER.SVME is 1, the RSM instruction is permitted to return to paged real mode (i.e.,CR0.PE=0 and CR0.PG=1).The AMD64 architecture uses a new 64-bit SMM state-save memory image.
This 64-bit save-statemap is used in all modes, regardless of mode. See “System-Management Mode” in Volume 2 fordetails.MnemonicRSMOpcodeDescription0F AAResume operation of an interrupted program.Related InstructionsNoneInstruction ReferenceRSM297AMD64 Technology24594—Rev. 3.13—July 2007rFLAGS AffectedAll flags are restored from the state-save map (SSM).IDVIPVIFACVMRFNTIOPLOFDFIFTFSFZFAFPFCFMMMMMMMMMMMMMMMMM2120191817161413–1211109876420Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified).
Unaffected flags areblank. Undefined flags are U.ExceptionsExceptionInvalid opcode, #UD298VirtualReal 8086 ProtectedXXXCause of ExceptionThe processor was not in System Management Mode (SMM).RSMInstruction Reference24594—Rev. 3.13—July 2007AMD64 TechnologySGDTStore Global Descriptor Table RegisterStores the global descriptor table register (GDTR) into the destination operand. In legacy andcompatibility mode, the destination operand is 6 bytes; in 64-bit mode, it is 10 bytes. In all modes,operand-size prefixes are ignored.In non-64-bit mode, the lower two bytes of the operand specify the 16-bit limit and the upper 4 bytesspecify the 32-bit base address.In 64-bit mode, the lower two bytes of the operand specify the 16-bit limit and the upper 8 bytesspecify the 64-bit base address.This instruction is intended for use in operating system software, but it can be used at any privilegelevel.MnemonicOpcodeDescriptionSGDT mem16:320F 01 /0Store global descriptor table register to memory.SGDT mem16:640F 01 /0Store global descriptor table register to memory.Related InstructionsSIDT, SLDT, STR, LGDT, LIDT, LLDT, LTRrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionInvalid opcode, #UDXXXThe operand was a register.Stack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceSGDT299AMD64 Technology24594—Rev.
3.13—July 2007SIDTStore Interrupt Descriptor Table RegisterStores the interrupt descriptor table register (IDTR) in the destination operand. In legacy andcompatibility mode, the destination operand is 6 bytes; in 64-bit mode it is 10 bytes. In all modes,operand-size prefixes are ignored.In non-64-bit mode, the lower two bytes of the operand specify the 16-bit limit and the upper 4 bytesspecify the 32-bit base address.In 64-bit mode, the lower two bytes of the operand specify the 16-bit limit and the upper 8 bytesspecify the 64-bit base address.This instruction is intended for use in operating system software, but it can be used at any privilegelevel.MnemonicOpcodeDescriptionSIDT mem16:320F 01 /1Store interrupt descriptor table register to memory.SIDT mem16:640F 01 /1Store interrupt descriptor table register to memory.Related InstructionsSGDT, SLDT, STR, LGDT, LIDT, LLDT, LTRrFLAGS AffectedNoneExceptionsExceptionVirtualReal 8086 ProtectedCause of ExceptionInvalid opcode, #UDXXXThe operand was a register.Stack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.XXXA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.XA null data segment was used to reference memory.General protection,#GPPage fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.300SIDTInstruction Reference24594—Rev.
3.13—July 2007AMD64 TechnologySKINITSecure Init and Jump with AttestationSecurely reinitializes the cpu, allowing for the startup of trusted software (such as a VMM). The codeto be executed after reinitialization can be verified based on a secure hash comparison. SKINIT takesthe physical base address of the SLB as its only input operand, in EAX.
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